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81. 发明授权

US5493505A Initializable asynchronous circuit design 失效
标题翻译：可初始化的异步电路设计
公开(公告)号：US5493505A
公开(公告)日：1996-02-20
申请号：US144802
申请日：1993-10-28
申请人： Savita Banerjee , Srimat T. Chakradhar , Rabindra K. Roy
发明人： Savita Banerjee , Srimat T. Chakradhar , Rabindra K. Roy
IPC分类号： G06F17/50 , H03K17/22
CPC分类号： G06F17/5059
摘要： A method of asynchronous circuit synthesis of initializable circuits from signal transition graphs (STG) that are either functionally initializable or functionally uninitializable is described. For functionally initializable cases, an initializable implementation can be achieved by proper assignment of don't care values. If the STG is not functionally initializable, the sources of uninitializability in the STG are identified and the STG is transformed into a functionally initializable specification by exploiting concurrency. Initializability is achieved at the expense of minimal removal of concurrency. Moreover, the transformation does not violate liveness and unique state coding properties of the STG. When the STG is functionally initializable or after an uninitializable STG is transformed to become functionally initializable the result is an initializable circuit design.
摘要翻译：描述了从功能可初始化或功能不可初始化的信号转换图（STG）的异步电路合成可初始化电路的方法。对于功能初始化的情况，可以通过正确分配无关值来实现可初始化的实现。如果STG不能在功能上初始化，则识别STG中不可初始化的来源，并通过利用并发将STG转换为功能可初始化的规范。可以以最小程度的并发删除为代价来实现初始化。此外，转换不会违反STG的活跃性和独特的状态编码性能。当STG在功能上可初始化时，或者在不可初始化的STG被变换成功能可初始化之后，结果是可初始化的电路设计。

82. 发明授权

US5359362A Videoconference system using a virtual camera image 失效
标题翻译：视频会议系统使用虚拟摄像机图像
公开(公告)号：US5359362A
公开(公告)日：1994-10-25
申请号：US40161
申请日：1993-03-30
申请人： John P. Lewis , Maximillian A. Ott , Ingemar J. Cox
发明人： John P. Lewis , Maximillian A. Ott , Ingemar J. Cox
IPC分类号： H04N7/15 , H04N7/00 , H04N7/14 , H04N7/12
CPC分类号： H04N7/142 , H04N7/002
摘要： A teleconferencing video system uses two cameras at each station symmetrically positioned on opposite sides of the optical axis between the speaker and the monitor used to produce an image of the listener. The two cameras are used to provide from the two images observed by the cameras a virtual image corresponding to the image that would be viewed by a camera located on the first-mentioned optical axis. This system permits eye contact to be maintained between a speaker and a listener at different stations whereby the feeling of intimacy is enhanced.
摘要翻译：电视会议视频系统在每个站处使用对称地位于扬声器和用于产生收听者的图像的监视器之间的光轴的相对侧上的两个摄像机。这两个摄像机用于从摄像机观察到的两个图像提供与由位于第一个提到的光轴上的照相机观看的图像相对应的虚像。该系统允许在不同站点的扬声器和收听者之间保持眼睛接触，从而增强亲密感。

83. 发明授权

US5355372A Threshold-based load balancing in ATM switches with parallel switch planes related applications 失效
标题翻译：具有并行交换平面相关应用的ATM交换机中基于阈值的负载平衡
公开(公告)号：US5355372A
公开(公告)日：1994-10-11
申请号：US107542
申请日：1993-08-17
申请人： Bhaskar Sengupta , Shyamal Chowdhury
发明人： Bhaskar Sengupta , Shyamal Chowdhury
IPC分类号： H04B10/02 , H04L12/56 , H04Q3/52 , H04L12/50 , H04L12/54
CPC分类号： H04L49/3081 , H04L49/1523 , H04L49/1553 , H04L49/50 , H04L2012/568 , H04L49/30
摘要： An asynchronous transfer mode switching system uses a parallel array of switching planes, distributors for distributing cells between the switching planes, and resequencers for collecting the cells after they have been switched. To balance the loads in the output buffers of the switching planes, each distributor includes two one-cell buffers and a load matrix. The load matrix stores the state of the output buffers in the switching planes, and this information is used to decide whether to send a cell arriving at the first of the one-cell buffers to its scheduled switching plane or to store the cell in the other of the one-cell buffers until either a switching plane with a lightly loaded output buffer for the cell's destination becomes available or another later arriving cell needs to be stored there.
摘要翻译：异步传输模式切换系统使用并行阵列的交换平面，用于在交换平面之间分配小区的分配器，以及用于在切换之后收集小区的调度器。为了平衡开关平面的输出缓冲器中的负载，每个分配器包括两个单电池缓冲器和负载矩阵。负载矩阵将输出缓冲器的状态存储在切换平面中，并且该信息用于决定是否将到达第一单电池缓冲器的单元发送到其调度的交换平面，或将该单元存储在另一个直到具有用于小区目的地的轻载输出缓冲器的切换平面变得可用，或者另一个后来到达的小区需要存储在那里。

84. 发明申请

US20040019859A1 Method and apparatus for efficient register-transfer level (RTL) power estimation 有权
标题翻译：用于有效的寄存器传输级（RTL）功率估计的方法和装置
公开(公告)号：US20040019859A1
公开(公告)日：2004-01-29
申请号：US10206672
申请日：2002-07-29
申请人： NEC USA, INC.
发明人： Srivaths Ravi , Anand Raghunathan , Srimat T. Chakradhar
IPC分类号： G06F017/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.
摘要翻译：用于加速电路的功率估计的技术包括产生电路的RTL描述。产生电路模型增强了电路的RTL描述。选择了一个模拟器。改进的功率模型增强RTL描述是为了使其更加友好的模拟器。运行模拟器来估计电路消耗的功率。还提供了使用延迟计算和分区采样的技术。还提供了使用上述技术领域的功率估计系统。

85. 发明申请

US20030216131A1 Active double-balanced mixer 有权
标题翻译：主动双平衡搅拌机
公开(公告)号：US20030216131A1
公开(公告)日：2003-11-20
申请号：US10144782
申请日：2002-05-15
申请人： NEC USA, INC.
发明人： Milan Kovacevic , Mohammad Madihian
IPC分类号： H04B001/26
CPC分类号： H03D7/1425 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/1491 , H03D2200/0043 , H03D2200/0047 , H03D2200/009
摘要： The present invention describes active double-balanced mixers. The mixers use an isolation and matching section that provides RF section input matching and superior isolation between the LO and RF port. The mixers can be implemented using an inexpensive semiconductor processing technology, obviating the need for matching inductors and facilitating a low-cost, low-power fully integrated wireless receiver.
摘要翻译：本发明描述了有源双平衡混合器。混频器使用隔离和匹配部分，提供RF部分输入匹配以及LO和RF端口之间的卓越隔离。可以使用廉价的半导体处理技术来实现混频器，从而避免了匹配电感器的需要并且促进低成本，低功率的完全集成的无线接收器。

86. 发明申请

US20030142818A1 Techniques for efficient security processing 审中-公开
标题翻译：高效安全处理技术
公开(公告)号：US20030142818A1
公开(公告)日：2003-07-31
申请号：US10259569
申请日：2002-09-30
申请人： NEC USA, INC.
发明人： Anand Raghunathan , Srivaths Ravi , Nachiketh Potlapally , Srimat Chakradhar , Murugan Sankaradas
IPC分类号： H04K003/00
CPC分类号： H04L63/0428 , G06F21/72 , H04L63/0485
摘要： A programmable security processor for efficient execution of security protocols, wherein the instruction set of the processor is enhanced to contain at least one instruction that is used to improve the efficiency of a public-key cryptographic algorithm, and at least one instruction that is used to improve the efficiency of a private-key cryptographic algorithm.
摘要翻译：一种用于有效执行安全协议的可编程安全处理器，其中所述处理器的指令集被增强以包含用于提高公开密钥密码算法的效率的至少一个指令，以及至少一个用于提高私密密码算法的效率。

87. 发明申请

US20030131216A1 Apparatus for one-cycle decompression of compressed data and methods of operation thereof 失效
标题翻译：用于压缩数据的一周期解压缩的装置及其操作方法
公开(公告)号：US20030131216A1
公开(公告)日：2003-07-10
申请号：US10135575
申请日：2002-05-01
申请人： NEC USA, INC.
发明人： Joerg Henkel , Haris Lekatsas , Venkata Jakkula
IPC分类号： G06F009/30
CPC分类号： G06F9/30178
摘要： Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.
摘要翻译：已知代码压缩是减少嵌入式系统指令存储器大小的有效技术。然而，代码压缩在提高处理器到存储器带宽方面也是非常有效的，因此提供了增加的系统性能。具有与解码电路和适当控制电路耦合的多个字典表的代码解压缩引擎耦合在处理器核心和指令高速缓存之间。代码解压缩引擎提供与未压缩指令混合的压缩指令的一周期解压缩，从而增加处理器到存储器的带宽并避免处理器停顿。

88. 发明申请

US20030105617A1 Hardware acceleration system for logic simulation 审中-公开
标题翻译：用于逻辑仿真的硬件加速系统
公开(公告)号：US20030105617A1
公开(公告)日：2003-06-05
申请号：US10102749
申请日：2002-03-22
申请人： NEC USA, INC.
发明人： Srihari Cadambi , Pranav Ashar
IPC分类号： G06F009/455
CPC分类号： G06F17/5027 , G06F17/5022
摘要： A hardware acceleration system for functional simulation comprising a generic circuit board including logic chips, and memory. The circuit board is capable of plugging onto a computing device. The system is adapted to allow the computing device to direct DMA transfers between the circuit board and a memory associated with the computing device. The circuit board is further capable of being configured with a simulation processor. The simulation processor is capable of being programmed for at least one circuit design.
摘要翻译：一种用于功能仿真的硬件加速系统，包括包含逻辑芯片和存储器的通用电路板。电路板能够插入计算设备。该系统适于允许计算设备在电路板和与计算设备相关联的存储器之间引导DMA传输。电路板还能够配置有仿真处理器。模拟处理器能够被编程为至少一个电路设计。

89. 发明申请

US20030063680A1 Per-bin DFE for advanced OQAM-based multi-carrier wireless data transmission systems 有权
标题翻译：用于基于OQAM的多载波无线数据传输系统
公开(公告)号：US20030063680A1
公开(公告)日：2003-04-03
申请号：US10076843
申请日：2002-02-19
申请人： NEC USA, INC.
发明人： Slobodan Nedic , Nenad Popovic
IPC分类号： H04K001/10 , H04L027/28 , H04B001/10
CPC分类号： H04L25/03159 , H04L2025/03414 , H04L2025/03611
摘要： An Apparatus for non-linear per-bin adaptive equalization in orthogonal multi-carrier data transmission systems with the Nyquist sub-channel spectral shaping and T/2 staggering of in-phase and quadrature components is disclosed. A previously introduced linear equalization embodiments are augmented by up to three, or more decision feed-back filters, to improve performance in presence of narrow-band interference (NBI) in wire-line and wire-less data transmission systems, and to enable exploitation of implicit diversity of multi-path fading channels, both with and without transmitter-end pre-coding. Adaptation properties of per-bin DFE equalization are analyzed by computer simulation for an intermediate number of constituent sub-channels. BER performance comparison between the conventional OFDM and OQAM-based multi-carrier systems of similar modulation/demodulation complexity and transmission latency is provided and the potential advantage of using spectrally well shaped orthogonal sub-channels in wireless applications is demonstrated.
摘要翻译：公开了一种具有奈奎斯特子信道频谱整形和同相和正交分量的T / 2交错的正交多载波数据传输系统中的非线性每箱自适应均衡的装置。先前引入的线性均衡实施例由多达三个或更多个判决反馈滤波器增强，以提高在有线和无线数据传输系统中存在窄带干扰（NBI）的性能，并且能够开发多路径衰落信道的隐含分集，具有和不具有发射机端预编码。通过计算机模拟分析中间数量的组成子通道来分析每箱DFE均衡的适应性。提供了具有类似调制/解调复杂性和传输延迟的传统OFDM和基于OQAM的多载波系统之间的BER性能比较，并且证明了在无线应用中使用频谱正确的正交子信道的潜在优点。

90. 发明申请

US20030058797A1 Path provisioning for service level agreements in differentiated service networks 失效
标题翻译：差异化服务网络中服务级别协议的路径配置
公开(公告)号：US20030058797A1
公开(公告)日：2003-03-27
申请号：US09897495
申请日：2001-07-03
申请人： NEC USA, INC.
发明人： Rauf Izmailov , Subir Biswas , Samrat Ganguly
IPC分类号： G01R031/00 , G08C015/00 , G06F011/00 , H04J001/16 , H04J003/14
CPC分类号： H04L45/00 , H04L41/12 , H04L41/5003 , H04L41/5019 , H04L45/124
摘要： A system and method for path provisioning in a network calculates an optimal path using a greedy algorithm with backtracking to execute service level agreements (SLAs). More specifically, a sequential path shifting (SPS) algorithm compares a cost of a suboptimal path for a present quadruplet with the cost of switching a path for a previous quadruplet configured for alteration. If the present path is already an optimal path, then no further operations are performed. However, if the cost of a suboptimal path is greater than the switching cost, the previous path is altered so that an optimal path may be configured for the present quadruplet. Otherwise, the present quadruplet maintains its existing path. The capacity of the network is iteratively adjusted to compensate for path selection. The present system may be applied to a differentiated services network or an optical network.
摘要翻译：用于网络中的路径配置的系统和方法使用具有回溯的贪心算法来计算最佳路径以执行服务水平协议（SLA）。更具体地，顺序路径移动（SPS）算法将当前四元组的次优路径的成本与为配置为改变的先前四元组的路径切换的成本进行比较。如果当前路径已经是最佳路径，则不再进行其他操作。然而，如果次优路径的成本大于切换成本，则改变先前的路径，以便为本发明的四元组配置最佳路径。否则，现在的四核维护其现有的路径。迭代地调整网络的容量以补偿路径选择。本系统可以应用于差分服务网络或光网络。

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