专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明专利

DE2401493C2 未知
公开(公告)号：DE2401493C2
公开(公告)日：1985-04-04
申请号：DE2401493
申请日：1974-01-12
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： KEENER, JOHN E., OKLAHOMA CITY, OKLA., US
IPC分类号： G09G1/16 , G06F3/153 , G09G1/00 , G09G5/18 , G09G5/22

82. 发明专利

DE3016819C2 未知
公开(公告)号：DE3016819C2
公开(公告)日：1984-12-20
申请号：DE3016819
申请日：1980-05-02
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： NIBBY JUN., CHESTER M., PEABODY, MASS., US , JOHNSON, ROBERT B., BILLERICA, MASS., US
IPC分类号： G06F1/04 , G06F1/06 , G06F3/00 , H03H7/30 , H03K5/15 , H03K5/14
摘要： A timing generator circuit includes a pair of multitap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between predetermined taps of the two delay lines to form a compensation network including a predetermined section of each delay line. The compensation network which operates to cancel out the effects of any mismatch resulting from connecting the delay lines in series.

83. 发明专利

DE2130372C2 未知
公开(公告)号：DE2130372C2
公开(公告)日：1984-06-07
申请号：DE2130372
申请日：1971-06-18
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： DELLICICCHI, ALFRED J., WEST NEWTON, MASS., US
IPC分类号： G11B20/14 , G11B5/02 , G06F1/04

84. 发明专利

DE2400048C2 未知
公开(公告)号：DE2400048C2
公开(公告)日：1984-05-10
申请号：DE2400048
申请日：1974-01-02
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： BORELLI, RONALD F., EDMONS, OKLA, US
IPC分类号： G03G15/05 , B41J2/39 , G03G15/32 , G06K15/14 , G11B9/08 , H04N1/29 , B41J3/18

85. 发明专利

AU534346B2 AUTOMATIC NOTE DISPENSER 未知
公开(公告)号：AU534346B2
公开(公告)日：1984-01-19
申请号：AU6434180
申请日：1980-11-13
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： GUIBORD RONALD D , HARMAN NEIL W , HENNESSY RICHARD E
IPC分类号： G07F9/00 , G06Q40/00 , G07D1/00 , G07F19/00 , G07F7/00
摘要： An automatic purge control for a banknote dispensing system including an operator panel having a keyboard for initiating transaction requests, a dispensing chamber adjacent to the panel for receiving banknotes dispensed in response to an operator request, a lockable access door to enable the operator to gain access to the chamber to remove dispensed notes, and a tiltable platform positioned within the chamber for discharging dispensed notes from the chamber under predetermined purge conditions detected by a microprocessor within the system. The microprocessor calls for a purge operation when it has been determined that the operator has either failed to remove dispensed notes or has left notes within the chamber. Interlocks are provided on the purge apparatus for inhibiting continued operation of the dispensing system if a purge cycle is improperly executed.

86. 发明专利

DE2264166C2 未知
公开(公告)号：DE2264166C2
公开(公告)日：1983-03-03
申请号：DE2264166
申请日：1972-12-29
申请人： HONEYWELL INFORMATION SYSTEMS INC., 02154 WALTHAM, MASS., US
发明人： NIBBY JUN., CHESTER M., NORTH BILLERICA, MASS., US , MANTON, JOHN C., MARLBORO, MASS., US , CURLEY, JOHN L., SUDBURY, MASS., US , FRANKLIN, BENJAMIN S., BOSTON, MASS., US
IPC分类号： G11C7/00 , G11C11/406
摘要： Apparatus and method for controlling the refreshing of volatile memory elements associated with data processing units. The invention minimizes the conflict between the memory refresh operation and the requirements for access to the memory elements during data processing operations. When conflict is unavoidable, it is resolved in favor of the refresh cycle to prevent loss of information. In memory elements of the type which are automatically refreshed during utilization by the data processing unit, a separate refresh cycle is eliminated when the utilization takes place in an appropriate interval.

87. 发明专利

DE2300186C2 未知
公开(公告)号：DE2300186C2
公开(公告)日：1982-04-15
申请号：DE2300186
申请日：1973-01-03
申请人： HONEYWELL INFORMATION SYSTEMS INC., 02154 WALTHAM, MASS., US
发明人： CROXON, BRIAN F., PEABODY, MASS., US
IPC分类号： G11C11/405 , G11C11/408 , H03K19/0185 , G11C7/00 , G11C8/00
摘要： 1417410 MOST gating circuits HONEYWELL INFORMATION SYSTEMS Inc 22 Dec 1972 [3 Jan 1972] 59462/72 Heading H3T [Also in Division G4] In a buffer drive circuit for a MOS memory system including an input gate 101, Fig. la, and an output driver 102, a first timing signal #1 is applied to initially condition the input gate 101 for sampling and storing an input signal Ao, to precharge the input circuit 102-14, 102-16 of the output driver 102 and to apply voltage signals of a first predetermined state to both output terminals Ao 1 , Ao 1 of the output driver 102 for the duration of the first timing signal and a second timing signal # 1 * is applied to condition the output driver 102 so as to select predetermined complementary states for signals on the output terminals Ao 1 , Ao 1 upon application of a third timing signal # 1 which applies the selected complementary drive signals to the output terminals Ao 1 and Ao 1 . In the buffer citcuit shown in Fig. 1a the first clock pulse #1 (Fig. 2, not shown) operates transistors 101-8 and 101-9 which sets the state of the transistors 102-2 and 102-6 so that the outputs Ao 1 and Ao 1 are at the first predetermined state. The state of the address input signal at Ao is stored on the capacitance 101-5 so that when the second clock pulse #1* occurs the transistor 102-2 or 102-6 is conditioned depending on the input information stored on the capacitance 101-5. The input at Ao is now represented by the voltage on the capacitances 102-16, 102-7 or 102-14, 102-3 and when the third clock pulse #1 is applied the transistor 102-2 and 102-8 or 102-6 and 102-4 change state to switch one of the output terminals Ao 1 or Ao 1 to the second state. Bootstrapping capacitors 102-3 and 102-7 are provided to enhance the switching speed of the transistor pairs 102-1, 102-5. Also the bootstrapping capacitors increase the conduction of the conducting one of the driver transistors 102-4, 102-8 such that the output level of Ao 1 , Ao 1 approximate the voltage level corresponding to the clock signal # 1 . The clock pulse sources # 1 * and #1 are derived from the clock pulses #1 in a clock inverter, Fig. 1b. The input clock pulses #1 are inverted by FET 110-1 to provide the clock pulses #1* and a capacitor 110-8 functions to provide a delay in turning off of FET's 110-4, 110-5 when the input clock pulse #1 is applied to provide a delayed clock pulse #1. A MOS memory chip is disclosed which uses the buffer circuits of Fig. 1a as Y and X select buffer circuits (100-1 to 100-11, Fig. 1, not shown). The outputs of the X and Y buffer circuits are applied via X and Y address decoder circuits (20-, 30) to condition one of transistors (60-1 to 60-32) and one of a selected pair of transistor circuits 70-1 to 70-15) so that information may be written into and read out of a selected FET memory cell (10) of an array of rows and columns of memory cells (10) via a digit/sense line (D/Sq to D/S32) by a write circuit (52) and a read circuit (92).

88. 发明专利

AU6062080A RECEIVER APPARATUS FOR OPTICALLY ENCODED DATA 未知
公开(公告)号：AU6062080A
公开(公告)日：1981-01-29
申请号：AU6062080
申请日：1980-07-18
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： PETRYK E M
IPC分类号： H04B10/00 , H03M5/12 , H04B10/152 , H04L5/22 , H04L25/49 , G06F3/04 , H04L25/50 , H04B9/00
摘要： An apparatus for receiving optically encoded binary data transmitted over an optical fiber from an optical transmitter device coupled to another data processing system. The receiver apparatus is used to convert the light signal carrying the subject data into TTL level digital logic signals. The receiver apparatus is comprised of circuitry for converting the optically encoded data into electrical signals in serial format, and circuitry for converting these electrical signals into TTL level digital signals in parallel format for use by a user device. The primary advantage of the apparatus disclosed here is the ability to substitute a single optical fiber for a plurality of parallel copper wires for carrying data between one data processing device and another with little or no loss in speed due to the larger bandwidth of optical fibers. Another significant advantage is the ability to couple data processing systems directly over much larger distances than possible with average cost parallel copper wire electrical cables. Higher noise immunity and communications security is also enjoyed. In the preferred embodiment, the receiver apparatus comprises a photodiode for converting the light signal into an electrical signal followed by an amplifier for changing the electrical signal to TTL digital logic levels. A clock generator and header detector recover a clock signal and detect the receipt of a header signal indicating transmission of a serial format data packet has commenced. A serial in and parallel out shift register/data latch storage buffer combination utilizes a signal derived from the recovered clock signal to shift the incoming data bits into the shift register and latch them into the data latch output buffers in parallel format when a counter signals that an entire data packet has been received.

89. 发明专利

AU5561380A DRILL MONITOR SYSTEM 未知
公开(公告)号：AU5561380A
公开(公告)日：1980-08-21
申请号：AU5561380
申请日：1980-02-15
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： BONE DALE H , SHIRES THOMAS J
IPC分类号： B23B47/18 , G05B19/4065 , G01L3/24 , G05B19/18 , G01L5/00 , B23B49/00
摘要： There is disclosed herein an apparatus for automatic monitoring of numerous high speed drill spindles on a numerically controlled drilling machine for purposes of immediate detection of the absence of drilling by a particular spindle because of a broken drill bit. The apparatus detects the absence of drilling, interrupts the automatic cycle of the drilling machine and alerts the operator. Power dissipation in each drill spindle motor is compared just prior to entry of the drill bit into the workpiece and after entry if any. If power dissipation increases above a predetermined threshhold level for all spindles, no interrupt is generated. If power dissipation does not increase in one or more spindle motors, comparator circuits alert a digital processor which interrupts automatic operation of the drilling machine and alerts the operator. Such a system eliminates the expense and error of human visual monitoring and generation of expensive scrap improperly processed before discovery of the broken bit.

90. 发明专利

AU3603378A APPARATUS FOR RECEIVING VARIABLE BYTE LENGTH DATA 未知
公开(公告)号：AU3603378A
公开(公告)日：1979-11-15
申请号：AU3603378
申请日：1978-05-11
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： DOWNEY DAVID L , KENNEDY JAMES A , NEELY LISTON E
IPC分类号： H03M7/00 , G06F13/00 , G06F13/12 , G06F13/38 , H04L1/00 , H04L23/00 , H04L25/38 , G06F1/00
摘要： An apparatus in a digital communication system for receiving and/or transmitting link control bytes of eight bits or in the alternative information bytes of any number of bits. Dynamic switching to different byte size in an information field is accomplished by utilizing a logic control field (LCF) as part of a message received or transmitted, comprising 8-bit bytes which are recursively extendable. The first octet of the LCF is a text control byte for identifying the number of bits in each byte contained in the accompanying text field transmitted or received, whereas the last LCF octet is indicated by setting the most significant bit (MSB) of the octet to 1. Apparatus responsive to the above fields for accomplishing the transition is disclosed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式