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81. 发明授权

US08216925B2 Transistor structure having a trench drain 有权
标题翻译：具有沟槽漏极的晶体管结构
公开(公告)号：US08216925B2
公开(公告)日：2012-07-10
申请号：US12917163
申请日：2010-11-01
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/94
CPC分类号： H01L29/0882 , H01L21/26586 , H01L29/0653 , H01L29/0661 , H01L29/0878 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/66727 , H01L29/7802 , H01L29/7811
摘要： A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.
摘要翻译：半导体器件形成为具有与器件的载流区相邻的沟槽。形成沟槽的深度大于装置的桶区域的深度。增加沟槽深度将较高场强的区域从桶区移动到沿着沟槽的区域。沿着沟槽的区域不具有接合点并且可以承受更高的场强。

82. 发明授权

US08125044B2 Semiconductor structure having a unidirectional and a bidirectional device and method of manufacture 有权
标题翻译：具有单向和双向装置的半导体结构及其制造方法
公开(公告)号：US08125044B2
公开(公告)日：2012-02-28
申请号：US12255429
申请日：2008-10-21
申请人： Bishnu P. Gogoi
发明人： Bishnu P. Gogoi
IPC分类号： H01L21/70
CPC分类号： H01L29/7803 , H01L21/2815 , H01L21/76208 , H01L21/823412 , H01L21/823456 , H01L21/823807 , H01L21/82385 , H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0922 , H01L29/0638 , H01L29/0657 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/42376 , H01L29/456 , H01L29/4941 , H01L29/66689 , H01L29/66719 , H01L29/7802 , H01L29/7816
摘要： In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.
摘要翻译：在各种实施例中，公开了制造这些结构的半导体结构和方法。在一个实施例中，一种方法包括同时在半导体材料中或其上形成单向晶体管的一部分和双向晶体管的一部分。描述和要求保护其他实施例。

83. 发明授权

US08076724B2 Transistor structure having an active region and a dielectric platform region 有权
标题翻译：具有有源区和电介质平台区的晶体管结构
公开(公告)号：US08076724B2
公开(公告)日：2011-12-13
申请号：US12248820
申请日：2008-10-09
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/7811 , H01L21/26586 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/41766 , H01L29/42376 , H01L29/66727
摘要： A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region (1300) and a dielectric platform region (1310). A trench (80) is formed adjacent to a drain (20) of the semiconductor device to a first depth. The etch process for forming trench (80) etches the dielectric platform region (1310) to a first depth. A second trench (210) is etched in trench (80) to further isolate areas in the active region (1300). The etch process for forming the second trench (210) etches the dielectric platform region (1310) to form a support structure for the dielectric platform in the substrate. The dielectric platform, the trench (80), and the second trench (210) is capped and sealed. The dielectric platform is made approximately planar to the major surface of the substrate by forming the support structure from the first depth to the second depth.
摘要翻译：形成具有较低栅 - 漏电容的半导体器件。具有有源区（1300）和电介质平台区（1310）的半导体器件。与半导体器件的漏极（20）相邻形成第一深度的沟槽（80）。用于形成沟槽（80）的蚀刻工艺将电介质平台区域（1310）蚀刻到第一深度。在沟槽（80）中蚀刻第二沟槽（210）以进一步隔离有源区域（1300）中的区域。用于形成第二沟槽（210）的蚀刻工艺蚀刻介电平台区域（1310）以形成用于衬底中的电介质平台的支撑结构。绝缘平台，沟槽（80）和第二沟槽（210）被封盖并密封。通过从第一深度到第二深度形成支撑结构，使电介质平台与基板的主表面大致平面。

84. 发明授权

US08063467B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08063467B2
公开(公告)日：2011-11-22
申请号：US12330748
申请日：2008-12-09
申请人： Michael Albert Tischler
发明人： Michael Albert Tischler
IPC分类号： H01L29/02
CPC分类号： H01L27/0617 , H01L21/76232 , H01L27/0629 , H01L27/08
摘要： In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed.
摘要翻译：在各种实施例中，公开了制造这些结构的半导体结构和方法。在一个实施例中，一种方法包括去除半导体材料的一部分以形成第一突起和具有在半导体材料的表面下方的边界的空腔，其中第一突起从腔的边界延伸。该方法还包括使用非保形材料的成角度沉积在第一突起的第一部分上形成非保形材料，其中非保形材料的沉积角度不垂直于半导体的表面材料。描述和要求保护其他实施例。

85. 发明授权

US08048760B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08048760B2
公开(公告)日：2011-11-01
申请号：US12833180
申请日：2010-07-09
申请人： Bishnu Prasanna Gogoi , Michael Albert Tischler
发明人： Bishnu Prasanna Gogoi , Michael Albert Tischler
IPC分类号： H01L29/06 , H01L21/764 , H01L21/768
CPC分类号： H01L21/76237 , H01L21/76232
摘要： In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.
摘要翻译：在各种实施例中，公开了制造这些结构的半导体结构和方法。在一个实施例中，结构包括电介质材料和衬底表面下的空隙。所述结构还包括在所述电介质材料上方的所述第一空隙上的掺杂电介质材料，其中所述电介质材料的至少一部分在所述衬底的至少一部分和所述掺杂电介质材料的至少一部分之间。描述和要求保护其他实施例。

86. 发明授权

US08008719B2 Transistor structure having dual shield layers 有权
标题翻译：具有双屏蔽层的晶体管结构
公开(公告)号：US08008719B2
公开(公告)日：2011-08-30
申请号：US12248811
申请日：2008-10-09
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/2815 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.
摘要翻译：形成具有较低栅极至漏极电容的半导体器件。邻近半导体器件的漏极（20）形成沟槽（80）。沟槽（80）具有侧壁表面（100）和表面（90）。通过沟槽（80）的侧壁表面（100）注入掺杂区域（110）。电介质层（150）覆盖在沟槽（80）的侧壁表面（100）上。屏蔽层（170）覆盖在电介质层（150）上。屏蔽层（170）位于漏极（20）的一部分和半导体器件的栅极和栅极互连的一部分之间，从而减小栅极至漏极电容。屏蔽层（170）覆盖沟槽（80）的表面（90）的少数部分。第二屏蔽层（270）进一步减小栅极至漏极电容。

87. 发明授权

US07985977B2 Sacrificial pillar dielectric platform 有权
标题翻译：牺牲支柱电介质平台
公开(公告)号：US07985977B2
公开(公告)日：2011-07-26
申请号：US12330765
申请日：2008-12-09
申请人： Bishnu Prasanna Gogoi , David William Wolfert, Jr.
发明人： Bishnu Prasanna Gogoi , David William Wolfert, Jr.
IPC分类号： H01L33/00
CPC分类号： H01L21/764 , H01L21/76224 , H01L2924/0002 , H01L2924/00
摘要： Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon.
摘要翻译：简而言之，根据一个或多个实施例，绝缘平台至少部分地形成在半导体衬底中并且至少部分地延伸到半导体衬底的表面之下。电介质平台可以包括通过回填在衬底中蚀刻的第一多个空腔而形成的结构柱，以及通过蚀刻掉设置在结构柱之间的牺牲柱而形成的第二多个空腔。第二多个空腔可以被封盖以密封第二多个空腔，以将包含在其中的材料（例如空气）的介电常数赋予介电平台的特性介电常数。或者，第二多个空腔可以用具有比衬底更低的介电常数的材料回填，例如二氧化硅，其中衬底包括硅。

88. 发明申请

US20100103578A1 ELECTRICAL STRESS PROTECTION APPARATUS AND METHOD OF MANUFACTURE 审中-公开
标题翻译：电力应力保护装置及其制造方法
公开(公告)号：US20100103578A1
公开(公告)日：2010-04-29
申请号：US12652839
申请日：2010-01-06
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H02H3/00
CPC分类号： H01L27/0262
摘要： In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar NPN transistor having a turn-on voltage of VBE2, and a field effect transistor (FET) having a threshold voltage of VTH, wherein a turn-on voltage VTO of the voltage transient protection device is approximately equal to the sum of VBE1, VBE2, and VTH, that is, VTO≅VBE1+VBE2+VTH. Other embodiments are described and claimed.
摘要翻译：在各种实施例中，公开了用于制造这些结构和装置的电路和半导体器件及其结构和方法。在一个实施例中，公开了双向极性电压瞬变保护装置。电压瞬变保护装置可以包括具有VBE1的导通电压的双极性PNP晶体管，具有VBE2导通电压的双极性NPN晶体管和具有阈值电压VTH的场效应晶体管（FET），其中a 电压瞬变保护装置的导通电压VTO近似等于VBE1，VBE2和VTH的总和，即VTO≅VBE1+ VBE2 + VTH。描述和要求保护其他实施例。

89. 发明授权

US07598588B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US07598588B2
公开(公告)日：2009-10-06
申请号：US11925457
申请日：2007-10-26
申请人： Robert Bruce Davies
发明人： Robert Bruce Davies
IPC分类号： H01L23/66
CPC分类号： H01L21/76232 , H01L21/76229 , H01L21/764 , H01L23/66 , H01L24/37 , H01L24/39 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6644 , H01L2224/371 , H01L2224/37599 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/49175 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor device includes a plurality of rectilinear structures, wherein the plurality of rectilinear structures comprise silicon dioxide and extend from a surface of a semiconductor material to a distance of at least about three microns or greater below the surface of the semiconductor material and wherein a first rectilinear structure of the plurality of rectilinear structures is perpendicular to, or substantially perpendicular to, a second rectilinear structure of the plurality of rectilinear structures. Other embodiments are described and claimed.
摘要翻译：在各种实施例中，公开了制造这些结构的半导体结构和方法。在一个实施例中，半导体器件包括多个直线结构，其中多个直线结构包括二氧化硅并且从半导体材料的表面延伸到半导体材料的表面以下至少约三微米或更大的距离并且其中所述多个直线结构的第一直线结构垂直于所述多个直线结构的第二直线结构或基本垂直于所述多个直线结构的第二直线结构。描述和要求保护其他实施例。

90. 发明申请

US20090152695A1 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：US20090152695A1
公开(公告)日：2009-06-18
申请号：US12392391
申请日：2009-02-25
申请人： Jeanne S. Pavio
发明人： Jeanne S. Pavio
IPC分类号： H01L23/495 , H01L23/36
CPC分类号： H01L24/81 , H01L23/047 , H01L23/3675 , H01L23/3737 , H01L23/49816 , H01L23/66 , H01L24/29 , H01L24/83 , H01L24/97 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/16 , H01L2224/2919 , H01L2224/73253 , H01L2224/81801 , H01L2224/83192 , H01L2224/83801 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/15787 , H01L2924/16152 , H01L2924/166 , H01L2924/3011 , Y10T29/49121 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor chip and a leadframe assembly. The heatsink also has a back surface from which a plurality of fins extend. The leadframe assembly includes a leadframe having leadframe leads extending from opposing sides of the leadframe to a central area of the leadframe. A liquid crystal polymer is disposed in a ring-shaped pattern on the leadframe leads. The liquid-crystal polymer is partially cured. The leadframe assembly is mounted on the front surface of the heatsink and the liquid crystal polymer is further cured to form a packaging assembly, which is then singulated into packaging substrates.
摘要翻译：具有安装在封装基板上的半导体芯片的半导体部件和使用批量处理步骤制造封装基板的半导体部件的制造方法。使用注射成型工艺形成散热器。散热器具有用于与半导体芯片和引线框架组件配合的前表面。散热片还具有多个翅片从该表面延伸的后表面。引线框架组件包括引线框架，该引线框架具有从引线框架的相对侧延伸到引线框架的中心区域的引线框引线。液晶聚合物以引线框架引线上的环状图案设置。液晶聚合物部分固化。引线框架组件安装在散热器的前表面上，并且液晶聚合物进一步固化以形成包装组件，然后将其包装成包装衬底。

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