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    • 71. 发明申请
      WO99034609A1 DUAL-LOOP PLL CIRCUIT AND CHROMINANCE DEMODULATION CIRCUIT USING THE SAME 审中-公开
    • DUAL-LOOP PLL CIRCUIT AND CHROMINANCE DEMODULATION CIRCUIT USING THE SAME
    • 双环锁相环电路和色差解调电路
    • WO99034609A1
    • 1999-07-08
    • PCT/JP1998/004915
    • 1998-10-30
    • H04N5/12 , H03L7/08 , H04N9/44 , H04N9/45 , H04N9/66
    • H04N9/66 , H04N9/45
    • A dual-loop PLL circuit is provided with a clamping circuit (12), an A/D converting circuit (14), a reference color burst outputting circuit (18), a PLL circuit (24), and a phase detecting circuit (34). The phase of a reference color burst KK outputted from the circuit (18) is changed at a slice level SL, and the level SL is changed by a reference phase value in the phase detecting circuit (34). The sampling clocks outputted from the PLL circuit (24) to the A/D converting circuit (14) are converted to a signal of a frequency of 4Fsc, and the phase of the signal can be changed continuously by using the reference phase value. In addition, since the phase of the sampling clocks can be adjusted to a desired value and the output signal of the A/D converting circuit (14) can be converted into a prescribed color difference signal by a signal conversion circuit and outputted, the color difference signals can be demodulated easily with high accuracy.
    • 双回路PLL电路具有钳位电路（12），A / D转换电路（14），参考色同步输出电路（18），PLL电路（24）和相位检测电路（34） ）。 从电路（18）输出的基准色同步信号KK的相位在限幅电平SL上变化，电平SL在相位检测电路（34）中变化为基准相位值。 从PLL电路（24）输出到A / D转换电路（14）的采样时钟被转换为4Fsc的频率的信号，并且可以通过使用参考相位值来连续地改变信号的相位。 此外，由于可以将采样时钟的相位调整到期望值，并且可以通过信号转换电路将A / D转换电路（14）的输出信号转换为规定的色差信号并输出​​，因此， 差分信号可以高精度地轻松解调。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 72. 发明公开
      EP1406390A1 PLL circuit and phase lock detector 失效
    • PLL circuit and phase lock detector
    • PLL电路和锁相检测器
    • EP1406390A1
    • 2004-04-07
    • EP03078676.8
    • 1998-01-19
    • SANYO ELECTRIC Co., Ltd.
    • Kiyose, Masashi c/o Sanyo Electric Co. Ltd. , Ito, Hiroya c/o Sanyo Electric Co. Ltd.
    • H03L7/089 , H03L7/095 , H04N9/45 , H03L7/10
    • H03L7/0997 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/10 , H03L7/107 , H04N9/45 , H04N11/146
    • A phase locked loop (PLL) circuit (70) for generating an oscillation clock which maintains a substantially constant phase difference with respect to a phase of a reference clock comprises
         a voltage controlled oscillator (107) receiving a control voltage and producing an oscillation clock having a frequency corresponding to the control voltage;
         a comparison circuit (12) receiving the reference clock and the oscillation clock and comparing phases of the reference clock and the oscillation clock with each other to produce a comparison signal indicative of a comparison result;
         a charge pump circuit (20), connected to said comparison circuit, a ground potential and a power supply potential, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the charge pump circuit pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential;
         a low-pass filter (30), connected between said charge pump circuit and said voltage controlled oscillator, for smoothing the output of the charge pump circuit to produce the control voltage;
         a lock detector (72) for receiving the reference clock and the oscillation clock, detecting if the oscillation clock maintains a substantially constant phase difference with respect to the phase of the reference clock and producing a detection signal indicative of a detection result; and
         a switch (71), connected to one of the input and output of said low-pass filter and responsive to the detection signal from said lock detector, the switch operating to supply one of the ground potential and the power supply potential to one of the input and output of said low-pass filter when the oscillation clock does not maintain a substantially constant phase difference with respect to the phase of the reference clock for at least a predetermined time.
    • 用于产生相对于参考时钟的相位保持基本上恒定的相位差的振荡时钟的锁相环（PLL）电路（70）包括接收控制电压并产生振荡时钟的振荡时钟的压控振荡器（107） 对应于控制电压的频率; 比较电路（12），接收参考时钟和振荡时钟并将参考时钟和振荡时钟的相位彼此比较以产生指示比较结果的比较信号; 连接到所述比较电路的电荷泵电路（20），接地电位和电源电位，用于接收比较信号，并且响应于比较信号选择接地电位和电源电位中的一个，其中， 当选择接地电位时，电荷泵电路从电荷泵电路的输出端子将恒定电流拉到地，并且当选择电源电位时向电荷泵电路的输出端子提供恒定电流，由此产生输出 交替地重复地电位和电源电位; 低通滤波器（30），连接在所述电荷泵电路和所述压控振荡器之间，用于平滑所述电荷泵电路的输出以产生所述控制电压; 锁定检测器（72），用于接收参考时钟和振荡时钟，检测振荡时钟相对于参考时钟的相位是否保持基本上恒定的相位差，并产生指示检测结果的检测信号; 和连接到所述低通滤波器的输入和输出之一并响应于来自所述锁定检测器的检测信号的开关（71），所述开关操作以将地电位和电源电位中的一个提供给 所述低通滤波器的输入和输出在所述振荡时钟相对于所述参考时钟的相位不保持基本恒定的相位差达至少预定时间时进行。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 79. 发明公开
      EP0247891A2 Phase locked loop system 失效
    • Phase locked loop system
    • Phasenregelkreissystem。
    • EP0247891A2
    • 1987-12-02
    • EP87304767.4
    • 1987-05-29
    • RCA Thomson Licensing Corporation
    • Balaban, Alvin Reuben , Demmer, Walter Heinrich , Patel, Chandrakant Bhailalbhai , Harwood, Leopold Albert
    • H03L7/08 , H04N9/455 , H04N9/89 , H04N9/45
    • H04N9/45 , H03L7/087
    • A phase locked loop is provided, which may be used in digital systems having clock signal frequency instabilities. The PLL has an analog oscillator (342) the frequency of which is determined by an analog control signal. The oscillatory signal is digitised (344) and phase-compared (338) with a digital reference signal, the digital output of the phase comparator being converted (340) to an analog signal to provide the oscillator control signal. In an application of the invention to a digital television receiver having a line-locked clock, the phase locked loop (350) regenerates two quadrature phase related subcarrier signals (COS,SIN) that are used to synchronously demodulate the chrominance signal components (CB) of the composite video signals into two color information signals (I,Q). The analog voltage-controlled oscillator (342) of the phase locked loop (350) generates a signal that is independent of any frequency instability in the line-locked clock signal. The analog-to-digital converter (344) digitizes this signal to provide one of the subcarrier signals, from which is generated the quadrature subcarrier signal, for example from a read-only memory (348). The two color information signals (I,Q) are obtained by multiplying (332,334) the chrominance signals by the first and second subcarrier signals. The phase comparator (336) determines the phase of the vector sum of the two color information signals and compares this against a desired phase value to generate a phase difference signal. The phase difference signal is filtered (338) and applied to the digital-to-analog converter (340) whichprovides the frequency control signal for the analog oscillator (342). A tracking filter (346) may be inserted at the output port of the analog-to-digital converter (344) to allow its quantization resolution to be reduced without affecting the performance of the phase locked loop.
    • 提供了锁相环，其可用于具有时钟信号频率不稳定性的数字系统中。 PLL具有模拟振荡器（342），其频率由模拟控制信号确定。 振荡信号用数字参考信号数字化（344）并进行相位比较（338），相位比较器的数字输出（340）转换为模拟信号以提供振荡器控制信号。 在将本发明应用于具有线锁时钟的数字电视接收机中，锁相环（350）再生用于同步解调彩色信号分量（CB）的两个正交相位相关副载波信号（COS，SIN） 的复合视频信号分成两个颜色信息信号（I，Q）。 锁相环（350）的模拟压控振荡器（342）产生独立于线锁定时钟信号中的任何频率不稳定性的信号。 模数转换器（344）将该信号数字化以提供例如从只读存储器（348）产生正交子载波信号的子载波信号之一。 通过将色度信号乘以（332,334）第一和第二子载波信号，获得两个颜色信息信号（I，Q）。 相位比较器（336）确定两个颜色信息信号的矢量和的相位，并将其与期望的相位值进行比较以产生相位差信号。 相位差信号被滤波（338）并且被施加到提供用于模拟振荡器（342）的频率控制信号的数模转换器（340）。 可以在模数转换器（344）的输出端口处插入跟踪滤波器（346），以允许其量化分辨率降低而不影响锁相环的性能。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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