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71. 发明申请

US20190149366A1 Serial Link Receiver with Improved Bandwidth and Accurate Eye Monitor 审中-公开
公开(公告)号：US20190149366A1
公开(公告)日：2019-05-16
申请号：US16161547
申请日：2018-10-16
申请人： Rambus Inc.
发明人： Marko Aleksic , Pravin Kumar Venkatesan , Simon Li , Nikhil Vaidya
IPC分类号： H04L25/03 , H04L1/00 , H03M13/21 , H03M13/00
CPC分类号： H04L25/03057 , H03M13/21 , H03M13/6502 , H04L1/0047 , H04L1/0057
摘要： A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

72. 发明授权

US10075290B2 Operator lifting in cryptographic algorithm 有权
公开(公告)号：US10075290B2
公开(公告)日：2018-09-11
申请号：US15104753
申请日：2014-12-17
申请人： KONINKLIJKE PHILIPS N.V.
发明人： Paulus Mathias Hubertus Mechtildis Antonius Gorissen , Ludovicus Marinus Gerardus Maria Tolhuizen
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , H04L9/06 , H03M13/23 , H03M13/21
CPC分类号： H04L9/008 , H03M13/21 , H03M13/23 , H04L9/0618 , H04L9/0631 , H04L9/0637 , H04L9/065 , H04L9/0656 , H04L9/0662 , H04L2209/04 , H04L2209/16
摘要： A system for performing an operation on data using obfuscated representations of the data is disclosed. Obtaining means are configured to obtain a first obfuscated representation of a first data value and obtain a second obfuscated representation of a second data value. A determining means 102 is configured to determine an obfuscated representation of a third data value, by performing the corresponding operations on the obfuscated representation of the first data value and the obfuscated representation of the second data value. Obfuscating means 101 may be configured to generate the first obfuscated representation based on the first data value and generate the second obfuscated representation based on the second data value. De-obfuscating means 103 may be configured to de-obfuscate the obfuscated representation of the third data value in order to obtain the third data value using a system of equations.

73. 发明申请

US20170250840A1 Serial Link Receiver with Improved Bandwidth and Accurate Eye Monitor 审中-公开
公开(公告)号：US20170250840A1
公开(公告)日：2017-08-31
申请号：US15438571
申请日：2017-02-21
申请人： Rambus Inc.
发明人： Marko Aleksic , Pravin Kumar Venkatesan , Simon Li , Nikhil Vaidya
IPC分类号： H04L25/03 , H03M13/00 , H04L1/00 , H03M13/21
CPC分类号： H04L25/03057 , H03M13/21 , H03M13/6502 , H04L1/0047 , H04L1/0057
摘要： A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

74. 发明申请

US20160233979A1 Method and System for Reliable Data Communications with Adaptive Multi-Dimensional Modulations for Variable-Iteration Decoding 审中-公开
标题翻译：用于可变迭代解码的自适应多维调制的可靠数据通信的方法和系统
公开(公告)号：US20160233979A1
公开(公告)日：2016-08-11
申请号：US14619392
申请日：2015-02-11
申请人： Mitsubishi Electric Research Laboratories, Inc.
发明人： Toshiaki Koike-Akino
IPC分类号： H04L1/00 , H03M13/11 , H03M13/39
CPC分类号： H03M13/116 , H03M13/036 , H03M13/1102 , H03M13/1111 , H03M13/1154 , H03M13/1191 , H03M13/136 , H03M13/138 , H03M13/1505 , H03M13/19 , H03M13/21 , H03M13/251 , H03M13/255 , H03M13/353 , H03M13/616 , H03M13/6325 , H03M13/6516 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0035 , H04L1/1829
摘要： In an advanced adaptive modulation and coding (AMC) scheme, the code rate and the parity-check matrix (PCM) for low-density parity-check (LDPC) codes are adapted according to modulation formats and variable-iteration receivers. The degree distribution for the PCM adaptation is designed by heuristic optimization to minimize the required SNR via an extrinsic information transfer (EXIT) trajectory analysis for finite-iteration decoding. The method uses dynamic window decoding by generating spatially coupled PCM for quasi-cyclic LDPC convolutional coding. The method also provides a way to jointly optimize labeling and decoding complexity for high-order and high-dimensional modulations. The problem to use a large number of different LDPC codes for various modulation formats and variable-iteration decoding is also dealt with by linearly dependent PCM adaptation across iteration count to keep using a common generator matrix. This PCM adaptation can improve a convergence speed of belief propagation decoding and mitigate an error floor issue.
摘要翻译：在高级自适应调制和编码（AMC）方案中，低密度奇偶校验（LDPC）码的码率和奇偶校验矩阵（PCM）根据调制格式和可变迭代接收机进行调整。通过启发式优化设计PCM适配的度分布，通过用于有限迭代解码的外部信息传递（EXIT）轨迹分析来最小化所需的SNR。该方法通过生成用于准循环LDPC卷积编码的空间耦合PCM来使用动态窗口解码。该方法还提供了一种共同优化标签和解码高阶和高维调制复杂度的方法。对于各种调制格式和可变迭代解码，使用大量不同LDPC码的问题也通过遍历计数的线性依赖的PCM适配来处理，以保持使用公共的发生器矩阵。这种PCM适配可以提高置信传播解码的收敛速度并减轻错误层次问题。

75. 发明授权

US09325349B2 Encoder, decoder and semiconductor device including the same 有权
标题翻译：编码器，解码器和包括其的半导体器件
公开(公告)号：US09325349B2
公开(公告)日：2016-04-26
申请号：US14254012
申请日：2014-04-16
申请人： SK hynix Inc.
发明人： Joon-Woo Kim , Hong-Sik Kim
IPC分类号： G06F11/10 , H03M13/21 , H03M13/13 , G11C11/56 , G11C13/00
CPC分类号： H03M13/21 , G11C11/5678 , G11C13/004 , H03M13/134
摘要： Provided is a semiconductor device configured to encode input data into a codeword including M different symbols, each of which includes Nm symbols. The semiconductor device including a first storage unit configured to store a first state value which is reset according to M and Nm; a second storage unit corresponding to any one of the M different symbols and configured to store M second state values determined through the corresponding symbol and the first state value; a third storage unit configured to store a third state value.
摘要翻译：提供了被配置为将输入数据编码成包括M个不同符号的码字的半导体器件，每个符号包括Nm个符号。所述半导体器件包括：第一存储单元，被配置为存储根据M和Nm复位的第一状态值; 对应于M个不同符号中的任何一个的第二存储单元，并且被配置为存储通过对应符号和第一状态值确定的M个第二状态值; 配置为存储第三状态值的第三存储单元。

76. 发明授权

US08949703B2 Parallel encoding for non-binary linear block code 有权
标题翻译：非二进制线性块代码的并行编码
公开(公告)号：US08949703B2
公开(公告)日：2015-02-03
申请号：US13430222
申请日：2012-03-26
申请人： Kalyana Krishnan , Hai-Jo Tarn
发明人： Kalyana Krishnan , Hai-Jo Tarn
IPC分类号： H03M13/00 , H03M13/13 , H03M13/11 , H03M13/05 , H03M13/21 , H03M13/15
CPC分类号： H03M13/13 , H03M13/05 , H03M13/1134 , H03M13/1137 , H03M13/1171 , H03M13/134 , H03M13/1515 , H03M13/21 , H03M13/6502 , H03M13/6561
摘要： An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.
摘要翻译：编码器模块包括顺序耦合的P / L奇偶校验移位寄存器，其中奇偶校验移位寄存器的第一奇偶移位寄存器的输入耦合到编码器模块的输入端，奇偶校验位的最后奇偶移位寄存器的输出移位寄存器耦合到编码器模块的输出，每个奇偶移位寄存器被配置为存储L个奇偶校验位。编码器模块还包括一个包括P / L奇偶校验生成模块的反馈电路，其中奇偶校验生成模块中的每一个通过开关耦合到奇偶移位寄存器中对应的一个的输出，并且还耦合到第一奇偶校验的输入移位寄存器，其中每个奇偶校验生成模块被配置为当其对应的开关闭合时，产生用于传输到第一奇偶移位寄存器的输入的L个奇偶校验位。

77. 发明申请

US20150019930A1 APPARATUS AND METHOD FOR DESIGNING QUANTUM CODE 有权
标题翻译：设计量子码的设备和方法
公开(公告)号：US20150019930A1
公开(公告)日：2015-01-15
申请号：US14377781
申请日：2012-02-21
申请人： Jun Heo , Jeong Hwan Shin
发明人： Jun Heo , Jeong Hwan Shin
IPC分类号： H03M13/13 , H03M13/00
CPC分类号： H03M13/13 , H03M13/033 , H03M13/05 , H03M13/21 , H03M13/615
摘要： Provided is an apparatus for designing a quantum code, which includes an analyzing unit for analyzing at least one quantum error generated in a quantum error channel as at least one binary error by using a standard form codeword stabilized quantum (CWS) code, a code generating unit for generating a binary error-correcting code which corrects the at least one binary error, a word operator generating unit for generating at least one word operator of the CWS code by using the at least one binary error-correcting code, and a codeword generating unit for generating at least one codeword including at least one entangled qubit (ebit) by using the at least one word operator.
摘要翻译：提供了一种用于设计量子码的装置，其包括分析单元，用于通过使用标准形式的码字稳定量子（CWS）码来分析在量子误差信道中产生的至少一个量子误差为至少一个二进制误差，用于产生校正所述至少一个二进制错误的二进制纠错码的单元，用于通过使用所述至少一个二进制纠错码产生所述CWS码的至少一个字操作符的字操作器生成单元，以及生成单元，用于通过使用所述至少一个字操作符来生成包括至少一个纠缠量子位（ebit）的至少一个码字。

78. 发明授权

US08862967B2 Statistical distribution based variable-bit error correction coding 有权
标题翻译：基于统计分布的可变位纠错编码
公开(公告)号：US08862967B2
公开(公告)日：2014-10-14
申请号：US13450963
申请日：2012-04-19
申请人： Deepak Pancholi , Manuel Antonio D'Abreu , Radhakrishnan Nair , Stephen Skala
发明人： Deepak Pancholi , Manuel Antonio D'Abreu , Radhakrishnan Nair , Stephen Skala
IPC分类号： H03M13/00 , G11C29/00 , H03M13/03 , H03M7/40 , H03M13/29 , H03M13/21 , H03M13/25 , H03M13/35 , H04N19/13 , H04N19/91
CPC分类号： H03M7/4093 , G06F11/1012 , H03M7/40 , H03M7/4031 , H03M7/405 , H03M13/00 , H03M13/21 , H03M13/25 , H03M13/255 , H03M13/258 , H03M13/2927 , H03M13/35 , H03M13/6318 , H04N19/13 , H04N19/91
摘要： A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.
摘要翻译：可以在包括存储器和控制器的数据存储设备执行方法。该方法包括向可变比特纠错编码（ECC）编码器提供用户数据。 ECC编码器产生第一组奇偶校验位。第一组奇偶校验位中的奇偶校验位的第一数量是基于存储的读错误计数确定的。该方法还包括将用户数据和第一组奇偶校验位存储到数据存储设备的存储器。

79. 发明授权

US08631308B2 Apparatus and method for determination of a position of a 1 bit error in a coded bit sequence, apparatus and method for correction of a 1-bit error in a coded bit sequence and decoder and method for decoding an incorrect, coded bit sequence 有权
标题翻译：用于确定编码比特序列中的1比特错误的位置的装置和方法，用于校正编码比特序列和解码器中的1比特错误的装置和方法以及用于对不正确的编码比特序列进行解码的方法
公开(公告)号：US08631308B2
公开(公告)日：2014-01-14
申请号：US13248502
申请日：2011-09-29
申请人： Michael Goessel , Michael Richter
发明人： Michael Goessel , Michael Richter
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/19 , H03M13/21 , H03M13/6502 , H03M13/6575
摘要： An apparatus for determination of a position of a 1-bit error includes an error position determiner of the inner code, an error syndrome determiner of the outer code, a derivative determiner and an overall error position determiner. The error position determiner of the inner code determines at least one possible error position of a bit error in the coded bit sequence on the basis of the inner code. The error syndrome determiner of the outer code determines a value of a non-linear syndrome bit of the outer code on the basis of a non-linear function of bits in the coded bit sequence. Furthermore, the derivative determiner determines a value of a derivative bit for at least one determined, possible error position of the bit error on the basis of derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence.
摘要翻译：用于确定1位错误位置的装置包括内码的错误位置确定器，外码的误差校正器确定器，导数确定器和总错误位置确定器。内部代码的错误位置确定器基于内部代码确定编码比特序列中的位错误的至少一个可能的错误位置。外码的误差校正器确定器基于编码比特序列中的比特的非线性函数来确定外码的非线性校正子比特的值。此外，导数确定器基于基于所确定的编码的可能错误位置中的位的非线性函数的导出，确定位误差的至少一个确定的可能错误位置的微分位的值。位序列。

80. 发明授权

US08483325B2 SISO decoder for a block code 有权
标题翻译： SISO解码器用于块代码
公开(公告)号：US08483325B2
公开(公告)日：2013-07-09
申请号：US12929434
申请日：2011-01-25
申请人： Chun-Chieh Tseng
发明人： Chun-Chieh Tseng
IPC分类号： H04L27/06
CPC分类号： H03M13/3784 , H03M13/1102 , H03M13/21 , H03M13/2906 , H03M13/451
摘要： A soft-in-soft-out (SISO) decoder for a general block code includes a source bit generator which generates k guessed source bits; a channel encoder which maps the k guessed source bits to an n-bit channel codeword; a QAM symbol mapper which generates a locally generated symbol sequence comprising m consecutive QAM symbols based on the n-bit channel codeword; a correlator which receives a symbol sequence, a channel state information sequence, and the locally generated symbol sequence to calculate a correlation associated with the received symbol sequence based on the received symbol sequence, the channel state information sequence, and the locally generated symbol sequence; and a log-likelihood ratio calculator which is connected to the source bit generator and the correlator to thereby calculate the required log-likelihood ratios associated with all coded bits corresponding to the received symbol sequence.
摘要翻译：用于通用块码的软进软（SISO）解码器包括产生k个猜测源比特的源比特发生器; 将k个猜测的源比特映射到n比特信道码字的信道编码器; QAM符号映射器，其基于所述n位信道码字生成包括m个连续QAM符号的本地生成的符号序列; 相关器，其接收符号序列，信道状态信息序列和本地生成的符号序列，以基于接收的符号序列，信道状态信息序列和本地产生的符号序列来计算与接收到的符号序列相关联的相关性; 以及对数似然比计算器，其连接到源比特发生器和相关器，从而计算与对应于所接收的符号序列的所有编码比特相关联的所需对数似然比。

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