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71. 发明申请

WO99029042A1 EFFICIENT ERROR CORRECTION IN PIPELINED ANALOG-TO-DIGITAL CONVERTERS 审中-公开
标题翻译：管道模拟数字转换器中的有效错误校正
公开(公告)号：WO99029042A1
公开(公告)日：1999-06-10
申请号：PCT/US1998/023135
申请日：1998-10-29
IPC分类号： H03M1/14 , H03M1/06 , H03M1/16
CPC分类号： H03M1/0695 , H03M1/0624 , H03M1/168
摘要： The present invention discloses a method and apparatus for correcting errors in N digital words generated by N+1 pipelined analog-to-digital converters. The method comprises the steps of: (1) synchronizing the N digital words by N groups of pipeline registers; and (2) correcting the synchronized N digital words by performing either an incrementing operation or a decrementing operation based on an adjustment value.
摘要翻译：本发明公开了一种用于校正由N + 1流水线模数转换器产生的N个数字字中的错误的方法和装置。该方法包括以下步骤：（1）通过N组流水线寄存器同步N个数字字; 和（2）通过执行基于调整值的递增运算或递减运算来校正同步的N个数字字。

72. 发明申请

WO2014030076A3 METHODS AND APPARATUS FOR CALIBRATING STAGES IN PIPELINE ANALOG-TO-DIGITAL CONVERTERS 审中-公开
标题翻译：管道模拟数字转换器中校准阶段的方法与装置
公开(公告)号：WO2014030076A3
公开(公告)日：2014-05-22
申请号：PCT/IB2013002609
申请日：2013-08-15
申请人： HITTITE MICROWAVE NORWAY AS
发明人： HERNES BJORNAR
IPC分类号： H03M1/10 , H03M1/06 , H03M1/16 , H03M1/44
CPC分类号： H03M1/1061 , H03M1/0695 , H03M1/167 , H03M1/442
摘要： A method and apparatus are provided for controlling calibration of a stage in a pipeline analog-to-digital converter.
摘要翻译：提供了一种用于控制管线模数转换器中的级的校准的方法和装置。

73. 发明申请

WO2012135700A1 PIPELINED ADC HAVING ERROR CORRECTION 审中-公开
标题翻译：管道误差修正的管道ADC
公开(公告)号：WO2012135700A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/031578
申请日：2012-03-30
申请人： ANALOG DEVICES, INC. , SIRAGUSA, Eric, John
发明人： SIRAGUSA, Eric, John
IPC分类号： H03M1/38
CPC分类号： H03M1/1009 , H03M1/0695 , H03M1/1033 , H03M1/168
摘要： A stage of a pipelined analog -to-digital converter can include first and second pluralities of digital-to-analog converters (DACs), the first plurality sufficient in number to produce a residue from the stage, the second plurality having their outputs added into an analog output of the stage. Mapping and calibration circuits can exchange inputs between selected ones of the first and second plurality of DACs, and provide first and second calibration signals to the selected one of the first plurality and another of the second plurality of DACs. The calibration signals can correlated to each other, but be uncorrelated to an analog input and digital output of the stage, and have unequal and partially offsetting effects on the stage's residue. A correction circuit can correct the digital output of the stage for circuit path errors based on a correlation between the calibration signals and an output of a succeeding stage.
摘要翻译：流水线模数转换器的级可以包括第一和第二多个数模转换器（DAC），第一个数量足以产生一个来自该级的残留，第二个多个具有加到其中的输出舞台的模拟输出。映射和校准电路可以在第一和第二多个DAC中的选定的DAC之间交换输入，并且向第二多个DAC中的第一和第二多个DAC中的所选择的一个提供第一和第二校准信号。校准信号可以彼此相关，但与舞台的模拟输入和数字输出不相关，并且对舞台的残留物具有不相等和部分抵消的影响。校正电路可以基于校准信号与后级的输出之间的相关性来校正电路路径误差的级的数字输出。

74. 发明申请

WO2010046831A1 PIPELINED ADC CALIBRATION 审中-公开
标题翻译：管道ADC校准
公开(公告)号：WO2010046831A1
公开(公告)日：2010-04-29
申请号：PCT/IB2009/054583
申请日：2009-10-19
申请人： NXP B.V. , ERDMANN, Christophe , BIALLAIS, A.
发明人： ERDMANN, Christophe , BIALLAIS, A.
IPC分类号： H03M1/10 , H03M5/22 , H03M1/06 , H03M1/16 , H03M1/80
CPC分类号： H03M1/1057 , H03M1/0695 , H03M1/164 , H03M1/804
摘要： A method of calibrating a pipelined analog to digital converter (400) having a plurality of DAC elements (410) and an additional calibration DAC element (420), in which a combination of positive, negative and zero reference voltages to the element under calibration and positive and negative reference voltages to the additional calibration DAC element to obtain four calibration states from which an error of the element under calibration is extracted by calculating an average of the difference between the four calibration states.
摘要翻译：一种校准具有多个DAC元件（410）和附加校准DAC元件（420）的流水线模数转换器（400）的方法，其中正，负和零参考电压组合到校准元件上，以及正和负参考电压到附加校准DAC元件，以获得四个校准状态，通过计算四个校准状态之间的差的平均值，从中提取校准元件的误差。

75. 发明申请

WO2005013495A2 SPACE EFFICIENT LOW POWER CYCLIC A/D CONVERTER 审中-公开
标题翻译：空间效率低功率循环A / D转换器
公开(公告)号：WO2005013495A2
公开(公告)日：2005-02-10
申请号：PCT/US2004/022511
申请日：2004-07-15
申请人： FREESCALE SEMICONDUCTOR, INC. , ATRISS, Ahmad, H. , ALLEN, Steven, P.
发明人： ATRISS, Ahmad, H. , ALLEN, Steven, P.
IPC分类号： H04B
CPC分类号： H03M1/0695 , H03M1/40
摘要： Methods and apparatus are provided for an analog converter (60). The apparatus comprises a first redundant signed digit (RSD) stage (62) and a configurable block (61). The configurable block (61) converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage (62). The first RSD stage (62) outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage (62) calculates a residue that is provided to the configurable block (61). The configurable block (61) is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block (61) is then converted back to a sample/hold circuit to start another conversion process.
摘要翻译：为模拟转换器（60）提供了方法和装置。该装置包括第一冗余有符号位（RSD）级（62）和可配置块（61）。可配置块（61）转换为采样/保持电路以对单端模拟信号进行采样。然后将采样的信号进行比例缩放，转换成差分信号并提供给第一RSD级（62）。第一RSD级（62）输出与数字信号的幅度对应的位值。在下一个半时钟周期中，第一RSD级（62）计算提供给可配置块（61）的残差。可配置块（61）被转换为第二冗余有符号数字级，并且产生对应于由第一RSD级提供的残差幅度的位值。第一和第二RSD级每个半时钟周期来回循环产生逻辑值，直到达到所需的位分辨率。然后将可配置块（61）转换回采样/保持电路以开始另一转换处理。

76. 发明申请

WO01095494A1 SELF-CALIBRATING ADC 审中-公开
标题翻译：自校准ADC
公开(公告)号：WO01095494A1
公开(公告)日：2001-12-13
申请号：PCT/US2001/018315
申请日：2001-06-06
IPC分类号： H03M1/06 , H03M1/44 , H03M1/14
CPC分类号： H03M1/0695 , H03M1/44
摘要： A pipeline ADC (100) includes an input stage (12) and a first group of subsequent stages, wherein the input stage includes a unity gain amplifier (16) having an input for receiving an analog input signal, an output, and first and second comparators (17A and 17B) each having a first input coupled to the output of the unity gain amplifier. The first comparator has a second input for receiving a first reference voltage an first output, and the second comparator has a second input for receiving a second reference voltage and an output. The input stage includes a full adder (40A) coupled to the output of the second comparator, and an output producing MSB bit information.
摘要翻译：流水线ADC（100）包括输入级（12）和第一组后级，其中输入级包括单位增益放大器（16），其具有用于接收模拟输入信号的输入端，输出端以及第一和第二级每个具有耦合到单位增益放大器的输出的第一输入的比较器（17A和17B）。第一比较器具有用于接收第一参考电压的第二输入的第一输出，而第二比较器具有用于接收第二参考电压和输出的第二输入。输入级包括耦合到第二比较器的输出的全加器（40A）和产生MSB位信息的输出。

77. 发明公开

EP3026818A1 METHOD OF CALIBRATING A SAR A/D CONVERTER AND SAR-A/D CONVERTER IMPLEMENTING SAID METHOD 有权转让
标题翻译：方法用于校准SAR模拟/数字转换器和SAR模拟/数字转换器用于所述方法的实现
公开(公告)号：EP3026818A1
公开(公告)日：2016-06-01
申请号：EP15189321.1
申请日：2015-10-12
申请人： STMicroelectronics S.r.l.
发明人： BURGIO, Carmelo , GIACOMINI, Mauro
IPC分类号： H03M1/10 , H03M1/46
CPC分类号： H03M1/1047 , H03M1/00 , H03M1/0695 , H03M1/1033 , H03M1/12 , H03M1/1245 , H03M1/462 , H03M1/466 , H03M1/687 , H03M1/802 , H03M1/804 , H03M1/806 , H03M1/808
摘要： The present disclosure relates to a method of self-calibration of a SAR-A/D converter, comprising a N bit -bit digital-to-analog converter (DAC) for outputting a N bit -bit output code, said digital-to-analog converter (DAC) comprising a first subconverter (C MSB ) having a plurality N Th of thermometer elements T j (1) and a second subconverter (C LSB ) having a plurality of binary-weighted elements N Bin , said output code being defined by a thermometer scale S Th having a number of levels equal to 2 NBitTh +1. The method is characterized in that it comprises the steps of:
- measuring, for each thermometer element of said plurality N Th of thermometer elements T j , an error value;
- determining a mean value (µ) of these values;
- dividing said plurality N Th of thermometer elements T j into a first subset (X) and a second subset (Y) each containing an identical number of values (x, y), equal to N Th /2, wherein said first subset (X) comprises the thermometer elements T j whose values are closer to said mean value (µ) as long as the error of the sum of thermometer elements T j of the first subset (X) is not worse than the error value of the element farthest from said mean value (µ) of said first subset (X) and said second subset (Y) comprising all the remaining thermometer elements T j ;
- generating said thermometer scale, on the assumption that:
- each level m i of said thermometer scale S Th , with i ranging from 0 to N Th /2, will be the incremental sum of each value (x) of said first ordered subset X;
- each further level m i of said thermometer scale S Th , with i ranging from N Th /2+1 to N Th , will be the sum of all the values (y) of said second subset Y plus the incremental sum of the elements (x) of the subset X in any order;
- generating said output code (OUTPUT) according to said thermometer scale S Th .
摘要翻译：本发明涉及一种SAR A / D转换器的自校准的方法，包括一个n位的位的数字 - 模拟转换器（DAC），用于输出一个廷n比特位输出代码，所述数字到模拟转换器（DAC），包括第一子转换器具有具有二进制加权元件的多元性温度计元件T J（1）的N个Th和第二子转换器（C LSB）（C MSB）N滨所述输出代码被定义通过温度计比例S的Th具有多个相等的水平，以2 NBitTh 1。该方法的特征在于，这样做是包括以下步骤： - 测量，为温度计元件T J，误差值的温度计，所述多个第N中的每个元件; - 确定性采矿平均值合成值（μ）; - 将温度计元件T j的所述多个n个成第一个子集（X）和第二子集（Y）各以等于第N / 2个值的数目相同（X，Y）含有worin所述第一子组（ X）包括温度计元件T J，其值更接近所述平均值（μ），只要所述第一子集（X）的温度计元件T j的总和的误差不大于所述元件最远的误差值差从所述平均值所述第一子组（X）和（μ）所述第二子组（Y），其包括所有剩余的温度计元件T J; - 产生所述温度计的规模，这样的假设： - 每个级别。所述温度计比例S的Th的MI，i的范围从0到N的Th / 2，将说第一有序子集X的每个值（X）的所述增量总和 ; - 说温度计比例S的Th的每此外水平MI，i的范围从第N / 2 + 1至第N，将所述第二子组Y加上元素的增量之和的所有值（Y）的总和（ x）的任何顺序的子集x的; - 所述产生雅丁到所述温度计比例S个输出码（OUTPUT）。

78. 发明公开

EP2037583A1 CONVERTER CIRCUIT, ANALOG/DIGITAL CONVERTER, AND METHOD FOR GENERATING DIGITAL SIGNALS CORRESPONDING TO ANALOG SIGNALS 有权
标题翻译：转换电路，用于产生模拟模拟数字转换器和方法的信号相应的数字信号
公开(公告)号：EP2037583A1
公开(公告)日：2009-03-18
申请号：EP07744949.4
申请日：2007-06-08
申请人： National University Corporation Shizuoka University
发明人： KAWAHITO, Shoji
IPC分类号： H03M1/14
CPC分类号： H03M1/1245 , H03M1/00 , H03M1/0604 , H03M1/0695 , H03M1/44
摘要： A charge corresponding to an analog signal V i is accumulated in first and second capacitors 25, 27, respectively. A digital signal V DIGN having a digital value (D 1 , D 0 , for example) corresponding to the analog signal V i is generated. By connecting the second capacitor 27 between an output 21c and an inversion input 21 a of an operational amplifier circuit 21 and supplying a first capacitor end 25a with an analog signal V D/A corresponding to the digital signal V DIGN , a first conversion value V OUT1 is generated in the output 21 c of the operational amplifier circuit 21. By connecting the first and third capacitors 25, 33 between the output 21 c and inversion input 21a of the operational amplifier circuit 21 and supplying a second capacitor end 27a with the analog signal V D/A , a second conversion value V OUT2 is generated in the output 21 c of the operational amplifier circuit 21.
摘要翻译：一批对应于模拟信号V i被分别累积在第一和第二电容器25,27。对应于所述模拟信号Vi的数字信号V DIGN具有数字值（D 1，D 0，例如）被生成。通过在输出21c的连接第二电容器27之间和到反演运算放大器电路21的输入端21a和对模拟信号VD提供第一电容器端部25a与/ A对应于数字信号V DIGN，第一转换值V OUT1 在运算放大器电路21的输出端21C中产生通过连接所述第一和第三电容器25，输出21c和运算放大器电路21的反相输入21a之间33和供给与所述模拟信号的第二电容器一端部27a VD / A，在运算放大电路21的输出端21C中产生第二转换值V OUT2

79. 发明公开

EP1917719A1 SWITCHED-CAPACITOR CIRCUIT WITH SCALED REFERENCE VOLTAGE 失效
标题翻译：带有刻度的参考电压切换电容器电路
公开(公告)号：EP1917719A1
公开(公告)日：2008-05-07
申请号：EP05856017.8
申请日：2005-12-30
申请人： Texas Instruments Incorporated
发明人： CORSI, Marco
IPC分类号： H03M1/38
CPC分类号： H03M1/08 , H03M1/0695 , H03M1/442
摘要： A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier. Sample capacitors and reference capacitors receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors are provided to maintain constant circuit gain. Extended reference voltages (VREFNX VREFNX) at levels that exceed the output range of the operational amplifier are applied to the reference capacitors, in response to the digital output of the analog-to-digital converter (23) in its stage (20). The reference capacitors are scaled according to the extent to which the extended reference voltages (VREFNX VREFNX) exceed the op amp output levels. The effects of noise on the reference voltages (VREFNX VREFNX) on the residue signal (RES) are thus greatly reduced.

80. 发明公开

EP1638208A1 Switched-capacitor circuit and pipelined A/D converter 有权
标题翻译： Schaltung mit geschaltetenKapazitätenund Pipeline-Analog-Digital-Wandler
公开(公告)号：EP1638208A1
公开(公告)日：2006-03-22
申请号：EP05251089.8
申请日：2005-02-24
申请人： FUJITSU LIMITED
发明人： Yoshioka, Masato, c/o Fujitsu Limited , Kudo, Masahiro, c/o Fujitsu Limited
IPC分类号： H03M1/12
CPC分类号： G11C27/026 , G11C27/024 , H03M1/0695 , H03M1/167 , H03M1/442
摘要： An input capacitor (CIN) and a plurality of reference capacitors (C1, C2) sample an input voltage (VIN) and reference voltages (+VR, -VR) in a first period. A switch circuit (S1 to S10) connects the input capacitor (CIN) and one of the reference capacitors (C1, C2) between an output and an input of an amplifier (DAMP) in a second period. This mechanism causes a feedback gain to be "1" in the second period. Therefore, it is possible to reduce power consumption and noise.
摘要翻译：输入电容器（CIN）和多个参考电容器（C1，C2）在第一周期中对输入电压（VIN）和参考电压（+ VR，-VR）进行采样。开关电路（S1至S10）在第二周期中将输入电容器（CIN）和参考电容器（C1，C2）中的一个在放大器（DAMP）的输出和输入之间连接。该机制在第二周期中使反馈增益为“1”。因此，可以降低功耗和噪声。

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