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71. 发明专利

JP4959931B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP4959931B2
公开(公告)日：2012-06-27
申请号：JP2004285023
申请日：2004-09-29
申请人：オンセミコンダクター・トレーディング・リミテッド
发明人：尚小倉
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0878 , H01L21/76213 , H01L21/823481 , H01L29/42368 , H01L29/4933 , H01L29/66681 , H01L29/7816

72. 发明专利

JP2011023429A Method of manufacturing semiconductor device, and semiconductor integrated circuit device 审中-公开
标题翻译：制造半导体器件的方法和半导体集成电路器件
公开(公告)号：JP2011023429A
公开(公告)日：2011-02-03
申请号：JP2009165084
申请日：2009-07-13
申请人： Mitsumi Electric Co Ltd , ミツミ電機株式会社
发明人： KASAHARA MASAKI
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/8249 , H01L21/266 , H01L21/76213 , H01L27/0623 , H01L29/732
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that uniformizes device characteristics by a simple process, and to provide a semiconductor integrated circuit device.
SOLUTION: The method of manufacturing the semiconductor device includes: a LOCOS oxide film forming step of forming a LOCOS oxide film 70 in a prescribed region 41 on the surface of a semiconductor substrate 40; a polysilicon forming step of forming a polysilicon film 90 so as to cover the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40; and an ion implantation step in which ions are implanted into the surface of the semiconductor substrate 40 while using the polysilicon film 90 as a mask so as to form an impurity region 60 on the surface of the semiconductor substrate 40.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过简单的工艺制造使器件特性均匀化的半导体器件的制造方法，并提供半导体集成电路器件。解决方案：制造半导体器件的方法包括：在半导体衬底40的表面上的规定区域41中形成LOCOS氧化膜70的LOCOS氧化膜形成步骤; 多晶硅形成步骤，形成多晶硅膜90以覆盖LOCOS氧化物膜70与半导体衬底40的表面之间的边界; 以及离子注入步骤，其中在使用多晶硅膜90作为掩模的同时将离子注入到半导体衬底40的表面中，以便在半导体衬底40的表面上形成杂质区60.权利要求（ C）2011，JPO＆INPIT

73. 发明专利

JP2006100578A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2006100578A
公开(公告)日：2006-04-13
申请号：JP2004285023
申请日：2004-09-29
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OGURA TAKASHI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0878 , H01L21/76213 , H01L21/823481 , H01L29/42368 , H01L29/4933 , H01L29/66681 , H01L29/7816
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can form a drain diffusion layer with high positional accuracy without being influenced by the shape etc. of a field oxide film.
SOLUTION: In the semiconductor device manufacturing method, a polysilicon film 9 and a silicon nitride film 10 are deposited on top face of an epitaxial layer 4. Then, the polysilicon film 9 and the silicon nitride film 10 are so patterned that they may be left over in a region where a LOCOS oxide film 14 is to be formed. Using a difference in level of the polysilicon film 9 and the silicon nitride film 10 as an alignment mark, a diffusion layer 11 is formed as a drain region. Thereafter, the LOCOS oxide film 14 is formed. By this manufacturing method, the diffusion layer 11 can be formed with high positional accuracy without being influenced by the shape of the LOCOS oxide film.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种可以在不受场氧化膜的形状等的影响的情况下以高位置精度形成漏极扩散层的半导体器件制造方法。解决方案：在半导体器件制造方法中，在外延层4的顶面上沉积多晶硅膜9和氮化硅膜10.然后，多晶硅膜9和氮化硅膜10被图案化，使得它们可以留在要形成LOCOS氧化物膜14的区域中。使用多晶硅膜9和氮化硅膜10的电平差作为对准标记，形成扩散层11作为漏区。此后，形成LOCOS氧化物膜14。通过该制造方法，扩散层11可以以高位置精度形成，而不受LOCOS氧化物膜的形状的影响。版权所有（C）2006，JPO＆NCIPI

74. 发明专利

JPS5780744A Method of producing integrated circuit 失效
公开(公告)号：JPS5780744A
公开(公告)日：1982-05-20
申请号：JP14403781
申请日：1981-09-14
申请人： Gen Electric
发明人： DARU MARIASU BURAUN , MARIO GETSUZO , KANGUURUNGU UONGU
IPC分类号： H01L29/78 , H01L21/265 , H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/26506 , H01L21/2652 , H01L21/31662 , H01L21/76213

75. 发明公开

KR1020100079144A 반도체 소자의 소자 분리막 형성 방법 无效
标题翻译：在半导体器件中形成隔离层的方法
公开(公告)号：KR1020100079144A
公开(公告)日：2010-07-08
申请号：KR1020080137559
申请日：2008-12-30
申请人： 주식회사 디비하이텍
发明人： 이종호
IPC分类号： H01L21/76
CPC分类号： H01L21/76213
摘要： PURPOSE: By using the mask formed into the size as much as the birds beak, the device isolating film forming method of the semiconductor device injects the oxygen ion into the field area. The birds beak domain is reduced. CONSTITUTION: An oxide film(302) and nitride film(304) are formed on the semiconductor substrate(300). In the formed oxide film as described above and nitride film, the domain in which the element isolation film is formed is etched. The photoresist pattern is formed on the oxide film and nitride film. The ion implantation operates in the domain in which the element isolation film is formed. The field oxide film(308) is formed after the removal of the formed photoresist pattern as described above.
摘要翻译：目的：通过使用形成为鸟喙大小的掩模，半导体器件的器件隔离膜形成方法将氧离子注入场区域。鸟喙域减少。构成：在半导体衬底（300）上形成氧化膜（302）和氮化物膜（304）。在如上所述形成的氧化物膜和氮化物膜中，蚀刻形成元件隔离膜的区域。在氧化物膜和氮化物膜上形成光致抗蚀剂图案。离子注入在其中形成元件隔离膜的区域中工作。如上所述，在去除形成的光致抗蚀剂图案之后形成场氧化膜（308）。

76. 发明公开

KR1020100074509A 반도체 소자의 소자 분리막 및 그 제조 방법 无效
标题翻译：半导体器件的隔离层及其制造方法
公开(公告)号：KR1020100074509A
公开(公告)日：2010-07-02
申请号：KR1020080132969
申请日：2008-12-24
申请人： 주식회사 디비하이텍
发明人： 김광용
IPC分类号： H01L21/762
CPC分类号： H01L21/76213
摘要： PURPOSE: An element isolation film of a semiconductor device and a method for manufacturing the same are provided to prevent the leakage current of an active region by preventing a bird-beak phenomenon from generating in the lower side of a nitride film. CONSTITUTION: A mask pattern is formed in a region of a semiconductor substrate in which a pad oxide film and an element isolation film are formed. Germanium ions are implanted into a semiconductor substrate through a space between the mask patterns and break the lattice of silicon in order to form barrier regions(16a, 16b). The mask pattern is removed, and a pad oxide film(20) and a nitride film are successively deposited on the semiconductor substrate. The pad oxide film and the nitride film are etched to expose a region on which the element isolation film is formed. A filed oxide film(50) which functions as the element isolation film is formed.
摘要翻译：目的：提供半导体器件的元件隔离膜及其制造方法，以通过防止在氮化膜的下侧产生鸟嘴现象来防止有源区的漏电流。构成：在形成有衬垫氧化膜和元件隔离膜的半导体衬底的区域中形成掩模图案。通过掩模图案之间的空间将锗离子注入到半导体衬底中，并且破坏硅的晶格以形成阻挡区（16a，16b）。去除掩模图案，并且在半导体衬底上依次沉积衬垫氧化膜（20）和氮化物膜。蚀刻衬垫氧化膜和氮化物膜以暴露其上形成元件隔离膜的区域。形成用作元件隔离膜的氧化膜（50）。

77. 发明公开

KR1019990088029A 산소주입후ＣＭＰ에의한얕은분리트렌치의형성방법 无效
标题翻译：通过CMP处理氧化物制备浅层隔离膜的方法
公开(公告)号：KR1019990088029A
公开(公告)日：1999-12-27
申请号：KR1019990015874
申请日：1999-05-03
申请人： 내셔널 세미콘덕터 코포레이션
发明人： 토마스마이클이 , 유안준
IPC分类号： H01L21/76
CPC分类号： H01L21/76213
摘要： 실리콘기판에얕은분리트렌치를형성하는방법에서는, 패터닝된 STI 마스크층을실리콘기판의상부표면상에직접형성한다. STI 마스크는기판의선택된상부표면영역을노출시킨다. 그후, 기판의노출시킨표면영역으로산소를주입하여주입된산소의영역을기판에한정시킨다. 그후, STI 마스크를제거하고기판의노출상부표면상에그리고산소가주입된영역내에실리콘이산화물을열 성장시킨다. 그후, 화학기계적연마를이용하여기판의상부표면으로부터여분의실리콘이산화물을제거함으로써, 평탄한표면을형성한다.

78. 发明授权

KR1019940001056B1 MOS트랜지스터의 제조방법 失效
标题翻译： MOS晶体管的制造方法
公开(公告)号：KR1019940001056B1
公开(公告)日：1994-02-08
申请号：KR1019860001316
申请日：1986-02-25
申请人： 인텔 코포레이션
发明人： 윌리엄베르그 , 치우에이치.팅 , 바이론비.슈 , 제이.씨.쯔엥
IPC分类号： H01L29/94
CPC分类号： H01L21/26533 , H01L21/76213 , H01L21/76243 , H01L21/76264 , H01L21/76267 , H01L21/76281 , H01L21/823814
摘要： MOS process for forming field-effect devices in self-alignment with a buried oxide region. Oxygen is implanted in alignment with masking members after gates have been defined from the masking members. The masking members block the oxygen implantation and thus the channel regions of subsequently formed transistors are self-aligned with openings in the buried oxide layer.

79. 发明申请

US20170117359A1 Bulk Nanosheet with Dielectric Isolation 有权
公开(公告)号：US20170117359A1
公开(公告)日：2017-04-27
申请号：US14919451
申请日：2015-10-21
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Bruce B. Doris , Junli Wang
IPC分类号： H01L29/06 , H01L21/762 , H01L21/265 , H01L27/12 , H01L29/10 , H01L29/66 , H01L21/84 , H01L21/02 , H01L29/167
CPC分类号： H01L29/0673 , H01L21/76213 , H01L21/7624 , H01L21/76281 , H01L21/845 , H01L27/1211 , H01L29/0665 , H01L29/1079 , H01L29/167 , H01L29/66439 , H01L29/66545
摘要： Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

80. 发明授权

US09373627B2 Multiple-time programming memory cells and methods for forming the same 有权
公开(公告)号：US09373627B2
公开(公告)日：2016-06-21
申请号：US14599791
申请日：2015-01-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Hung Fu , Chun-Yao Ko , Tuo-Hsin Chien , Ting-Chen Hsu
IPC分类号： H01L29/788 , H01L27/115 , G11C16/04 , H01L21/762 , H01L29/423 , H01L29/66 , H01L21/02 , H01L21/265 , H01L21/28 , H01L21/306 , H01L21/3205 , H01L49/02
CPC分类号： H01L27/11521 , G11C16/0408 , H01L21/0223 , H01L21/265 , H01L21/28273 , H01L21/30604 , H01L21/32055 , H01L21/76205 , H01L21/76213 , H01L21/76224 , H01L21/76237 , H01L27/11517 , H01L27/11558 , H01L28/40 , H01L28/60 , H01L29/42324 , H01L29/66825
摘要： A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

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