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71. 发明申请

US20090116316A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US20090116316A1
公开(公告)日：2009-05-07
申请号：US12134865
申请日：2008-06-06
申请人： Jeong-Yoon Ahn , Ji-Eun Jang , Young-Jun Ku
发明人： Jeong-Yoon Ahn , Ji-Eun Jang , Young-Jun Ku
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/46 , G11C29/02 , G11C29/025 , G11C29/1201 , G11C2029/1206
摘要： Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-off units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.
摘要翻译：半导体器件和半导体存储器件包括多个内部电路，其被配置为响应于它们各自的测试模式信号执行测试操作;以及多个测试单元，被配置为响应于一个或多个测试模式控制内部电路的测试操作被禁用测试信号。

72. 发明授权

US07521950B2 Wafer level I/O test and repair enabled by I/O layer 失效
标题翻译：通过I / O层启用晶圆级I / O测试和修复
公开(公告)号：US07521950B2
公开(公告)日：2009-04-21
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/00 , G01N37/00 , G06F13/20 , G06F13/36 , G06F11/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

73. 发明申请

US20070152700A1 System and method for testing one or more dies on a semiconductor wafer 有权
标题翻译：用于测试半导体晶片上的一个或多个管芯的系统和方法
公开(公告)号：US20070152700A1
公开(公告)日：2007-07-05
申请号：US11707408
申请日：2007-02-16
申请人： David Ma , Tao Wang , James Dietz , Bing Ren
发明人： David Ma , Tao Wang , James Dietz , Bing Ren
IPC分类号： G01R31/26
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
摘要翻译：测试系统或方法将半导体晶片中的一个或多个管芯的读取数据与写入一个或多个管芯的原始数据进行比较。测试系统包括连接到半导体晶片上的一个或多个管芯的一个或多个写入寄存器。一个或多个比较器连接到管芯和写入寄存器。比较器响应原始数据和读取数据产生结果。

74. 发明申请

US20070002649A1 Area efficient memory architecture with decoder self test and debug capability 有权
标题翻译：具有解码器自检和调试功能的区域高效存储器架构
公开(公告)号：US20070002649A1
公开(公告)日：2007-01-04
申请号：US11437420
申请日：2006-05-18
申请人： Prashant Dubey
发明人： Prashant Dubey
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C5/025 , G11C29/024 , G11C2029/1206
摘要： An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.
摘要翻译：集成的测试设备减少了存储器的外部布线拥塞。集成测试设备提供单独的解码器测试和调试来查找存储器中的特定错误。该器件还有助于降低外部BIST测试的复杂性。此外，N寻址存储器的解码器测试所需的时钟周期数从4N周期减少到N个时钟周期。此外，随着测试设备在正常操作模式下用作流水线设备，存储器的访问时间减少。

75. 发明授权

US07107504B2 Test apparatus for semiconductor device 有权
公开(公告)号：US07107504B2
公开(公告)日：2006-09-12
申请号：US10073129
申请日：2002-02-13
申请人： Masahiro Sato , Junji Akaza , Nobumi Kodama , Hirohisa Mizuno , Takashi Imura , Yasurou Matsuzaki
发明人： Masahiro Sato , Junji Akaza , Nobumi Kodama , Hirohisa Mizuno , Takashi Imura , Yasurou Matsuzaki
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/50012 , G11C29/006 , G11C29/36 , G11C2029/1206
摘要： A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.

76. 发明申请

US20060158209A1 System and method for testing one or more dies on a semiconductor wafer 有权
公开(公告)号：US20060158209A1
公开(公告)日：2006-07-20
申请号：US11386512
申请日：2006-03-22
申请人： David Ma , Tao Wang , James Dietz , Bing Ren
发明人： David Ma , Tao Wang , James Dietz , Bing Ren
IPC分类号： G01R31/02
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

77. 发明申请

US20060132167A1 Contactless wafer level burn-in 审中-公开
标题翻译：非接触晶片级老化
公开(公告)号：US20060132167A1
公开(公告)日：2006-06-22
申请号：US11021688
申请日：2004-12-22
申请人： Jian Chen
发明人： Jian Chen
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2856 , G01R31/2862 , G01R31/3025 , G11C16/04 , G11C29/006 , G11C29/06 , G11C2029/1206 , G11C2029/5602
摘要： A method and apparatus for performing a wafer-level burn-in. The method comprises the steps of providing the wafer into a burn-in chamber; and outputting a power and a test initiation signal to a wafer via a wireless signal. The apparatus includes a test chamber, a transport mechanism in the test chamber, a temperature control apparatus in the test chamber, and an RF transponder in the chamber.
摘要翻译：一种用于进行晶片级老化的方法和装置。该方法包括以下步骤：将晶片提供到老化室; 并通过无线信号向晶片输出功率和测试启动信号。该装置包括测试室，测试室中的传送机构，测试室中的温度控制装置和室中的RF应答器。

78. 发明申请

US20050223289A1 SEMICONDUCTOR EMBEDDED MEMORY DEVICES HAVING BIST CIRCUIT SITUATED UNDER THE BONDING PADS 审中-公开
标题翻译：半导体嵌入式嵌入式存储器件，具有接线柱下方的BIST电路
公开(公告)号：US20050223289A1
公开(公告)日：2005-10-06
申请号：US10708762
申请日：2004-03-24
申请人： Ming-Jing HO
发明人： Ming-Jing HO
IPC分类号： G06F11/00 , G11C5/02 , G11C29/12
CPC分类号： G11C5/025 , G11C29/12 , G11C2029/0401 , G11C2029/1206
摘要： An embedded memory chip having BIST (built-in self test) circuit under pad is disclosed. The embedded memory chip includes a logic circuit and a memory unit coupled to the logic circuit. The logic circuit and memory unit are fabricated substantially in a center area of the embedded memory chip. A number of bonding pads are situated on a peripheral area adjacent to the center area of the embedded memory chip. The BIST circuit is situated directly under at least one of the bonding pads. The BIST circuit is activated when implementing an IC testing on the embedded memory chip for detecting faults in the memory unit and is deactivated as a disuse part of the embedded memory chip after finishing the IC testing.
摘要翻译：公开了一种在垫下具有BIST（内置自检）电路的嵌入式存储芯片。嵌入式存储器芯片包括逻辑电路和耦合到逻辑电路的存储器单元。逻辑电路和存储单元基本上在嵌入式存储芯片的中心区域中制造。多个接合焊盘位于与嵌入式存储芯片的中心区域相邻的外围区域上。 BIST电路直接位于至少一个接合焊盘下方。当在嵌入式存储器芯片上进行IC测试以检测存储器单元中的故障时，BIST电路被激活，并且在完成IC测试之后被禁用作为嵌入式存储器芯片的废弃部分。

79. 发明授权

US06587979B1 Partitionable embedded circuit test system for integrated circuit 失效
标题翻译：集成电路分区嵌入式电路测试系统
公开(公告)号：US06587979B1
公开(公告)日：2003-07-01
申请号：US09494824
申请日：2000-01-31
申请人： Lawrence Kraus , Ivan-Pierre Batinic , Marc P. Loranger , Hiralal Ranga
发明人： Lawrence Kraus , Ivan-Pierre Batinic , Marc P. Loranger , Hiralal Ranga
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C29/46 , G11C2029/1206 , G11C2207/104
摘要： A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.
摘要翻译：灵活的内置自检（BIST）电路被集成到集成电路（IC）中，用于测试嵌入在集成电路中的一个或随机存取存储器或其他存储器，而不管存储器的数量，尺寸或测试要求如何。来自控制器的输入数据可以方便地在IC内部和外部的组件之间分配，向BIST电路提供数据，指示要测试的嵌入式存储器的大小，并从多种BIST操作模式中进行选择。

80. 发明申请

US20030081490A1 Semiconductor memory device allowing high density structure or high performance 有权
标题翻译：半导体存储器件允许高密度结构或高性能
公开(公告)号：US20030081490A1
公开(公告)日：2003-05-01
申请号：US10126622
申请日：2002-04-22
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Tsutomu Nagasawa , Hideki Yonetani , Kozo Ishida , Shinichi Jinbo , Makoto Suwa , Tadaaki Yamauchi , Junko Matsumoto , Zengcheng Tian , Takeo Okamoto
IPC分类号： G11C008/00
CPC分类号： G11C29/12005 , G11C8/12 , G11C29/26 , G11C2029/1206
摘要： A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.
摘要翻译：半导体存储器件包括存储体，预解码器，锁存电路，计数器，熔丝和缓冲器。存储体包括以行和列排列的多个存储单元。预解码器设置在半导体存储器件的中心部分。预解码器基于从缓冲器接收到的存储体地址产生用于选择每个存储体的预解码信号，并将预解码信号输出到存储体。预解码器产生用于基于存储体地址选择每个存储体的预解码信号，并将预解码信号输出到存储体。因此，可以减少中心部分的互连。

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