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71. 发明公开

EP1188108A1 TWO CLOCK DOMAIN PULSE TO PULSE SYNCHRONIZER 有权
标题翻译：电路用以下两种不同的时钟相互SCOPE生产的同步脉冲
公开(公告)号：EP1188108A1
公开(公告)日：2002-03-20
申请号：EP00925576.1
申请日：2000-04-17
申请人： Italtel S.p.a.
发明人： GEMELLI, Riccardo , PAVESI, Marco
IPC分类号： G06F5/06
CPC分类号： G06F5/06 , G06F2205/102 , H04L7/02
摘要： A synchronization circuit (P2P) for interfacing a first digital circuit functioning with a first clock (CLK1) and a second digital circuit functioning with a second clock (CLK2) that may be different from the first clock (CLK1) in terms of frequency and/or phase is constituted by a transmitting section functioning with the first clock (CLK1), a receiving section functioning with the second clock (CLK2) and a feedback section functioning with the first clock (CLK1). A bidirectional synchronizer transfers commands with a strobe signal (STR) from a microprocessor interface (MPRI) functioning with the first clock (CLK1) to an application circuit (APL) functioning with the second clock (CLK2) and alarm signals from the application circuit (APL) to the microprocessor interface (MPRI).

72. 发明公开

EP0339797A3 Method and apparatus for nodes in network to avoid shrinkage of an interframe gap 失效
标题翻译：网络节点的方法和装置避免了帧间隙的收敛
公开(公告)号：EP0339797A3
公开(公告)日：1992-06-03
申请号：EP89303074.2
申请日：1989-03-29
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kaufman, Charles , Hutchison, Jerry , Kempf, Mark
IPC分类号： H04J3/06 , H04L12/42
CPC分类号： H04L25/05 , G06F2205/102 , H04J3/0632
摘要： An output controller in a repeater node for controlling data transfers in a data communication system in which each node is operated by an independent local clock. Nodes will occasionally delete idle bytes from a preamble to recenter an elasticity buffer. The output controller performs a process that requires the elasticity buffer to be progressively more full before deleting another idle byte from the preamble. Tranmission of the start of a subsequent frame is delayed and additional idle bytes are transmitted when the number of idle bytes being transmitted is at or below a certain threshold. Multiple thresholds are utilized so that the amount of the delay can be adjusted.

73. 发明公开

EP0396669A1 METHOD AND APPARATUS FOR DETECTING IMPENDING OVERFLOW AND/OR UNDERRUN OF ELASTICITY BUFFER 有权
标题翻译：方法和系统紧急的知觉堰和/或后面一个灵活的缓冲区的事件。
公开(公告)号：EP0396669A1
公开(公告)日：1990-11-14
申请号：EP89910751.0
申请日：1989-04-26
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： IANNARONE, John, R. , THOMPSON, Bruce, W.
IPC分类号： G06F5 , H04J3 , H04L7
CPC分类号： G06F5/14 , G06F2205/102 , H04J3/0632
摘要： L'invention concerne un tampon d'élasticité asynchrone. La sélection de l'adresse ou d'un élément de stockage pour l'écriture ou la lecture de données est exécutée par des pointeurs d'entrée et de sortie asynchrones mis en oeuvre à l'aide de compteurs de codes binaires réfléchis circulaires. Le tampon est initialisé une fois pendant la transmission de chaque bloc de données de sorte que les pointeurs ne sélectionnent pas le même élément de stockage pour l'écriture et la lecture en même temps. Le dépassement de capacité d'écriture ou l'insuffisance de lecture d'un élément de stockage est détecté avant qu'une éventuelle altération de données ne puisse se produire, par comparaison entre les pointeurs d'entrée et de sortie. Un état d'erreur est détecté si les pointeurs d'entrée et de sortie se chevauchent pendant une période de seuil pouvant être plus courte que la période requise pour l'écriture ou la lecture d'une unité de données multibits dans le tampon et inversement. La période de temps de chevauchement est déterminée par comparaison des pointeurs à un ou plusieurs temps d'échantillonnage correspondant à des phases sélectionnées d'un signal d'horloge.

74. 发明授权

EP0217486B1 A synchronizing system 失效
标题翻译：同步系统
公开(公告)号：EP0217486B1
公开(公告)日：1990-10-03
申请号：EP86304507.6
申请日：1986-06-12
申请人： Hewlett-Packard Company
发明人： Nordby, Rasmus , Crandall, Douglas
IPC分类号： G06F13/42 , H04L7/00 , G06F5/06
CPC分类号： G06F5/10 , G06F13/4243 , G06F2205/102

75. 发明申请

US20150186113A1 DATA TRANSFER BETWEEN CLOCK DOMAINS 审中-公开
标题翻译：时钟域之间的数据传输
公开(公告)号：US20150186113A1
公开(公告)日：2015-07-02
申请号：US14409985
申请日：2013-06-20
申请人： NORDIC SEMICONDUCTOR ASA
发明人： Per Carsten Skoglund , Asghar Havashki , Arne Wanvik Venas , Asmund Holen , Markus Bakka Hjerto
IPC分类号： G06F5/06
CPC分类号： G06F5/06 , G06F2205/061 , G06F2205/102
摘要： An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).
摘要翻译：一种用于在数字系统中将数据信号（data_a）从第一时钟域（2）传送到第二时钟域（4）的装置。该装置具有用于从第一时钟域（2）接收输入信号（data_a）的信号输入（6,7），用于存储输入信号（data_a）的装置（6,7）和装置（12,13）用于在第二时钟域（4）的时钟信号（ck）中的转变之后将输入信号（data_a）传送到第二时钟域（4）。

76. 发明授权

US08918666B2 Apparatus for synchronizing a data handover between a first and second clock domain through FIFO buffering 有权
标题翻译：用于通过FIFO缓冲在第一和第二时钟域之间同步数据切换的装置
公开(公告)号：US08918666B2
公开(公告)日：2014-12-23
申请号：US13113730
申请日：2011-05-23
申请人： Thomas Bauernfeind , Stephan Henzler
发明人： Thomas Bauernfeind , Stephan Henzler
IPC分类号： H04L7/00
CPC分类号： H04L7/005 , G06F5/12 , G06F2205/061 , G06F2205/102 , H04L7/0012
摘要： An apparatus for synchronizing a data handover between a first clock domain and a second clock domain includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage receives an input data value in synchronization with the first clock domain and provides an output data value in synchronization with the second clock domain in response to a current synchronization pulse. The fill level information provider provides fill level information describing a fill level of the FIFO. The feedback path feeds back the fill level information to the calculator to adjust the synchronization pulse cycle duration information.
摘要翻译：一种用于在第一时钟域和第二时钟域之间同步数据切换的装置包括计算器，先进先出存储器，同步脉冲发生器，填充级别信息提供器和反馈路径。计算器被配置为提供描述在第二时钟域的时钟处的同步脉冲的时间位置的同步脉冲周期持续时间信息。先进先出存储器与第一时钟域同步地接收输入数据值，并响应于当前同步脉冲提供与第二时钟域同步的输出数据值。填充级别信息提供者提供描述FIFO的填充级别的填充级别信息。反馈路径将填充水平信息反馈到计算器以调整同步脉冲周期持续时间信息。

77. 发明授权

US08898502B2 Clock domain crossing interface 有权
标题翻译：时钟域交叉界面
公开(公告)号：US08898502B2
公开(公告)日：2014-11-25
申请号：US13176160
申请日：2011-07-05
申请人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
发明人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
IPC分类号： G06F1/12 , H04L7/02 , G06F5/10
CPC分类号： G06F1/12 , G06F5/10 , G06F2205/102 , H04L7/005 , H04L7/02
摘要： A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.
摘要翻译：在SoC设备的时钟域之间提供灵活且可扩展的双向CDC接口。接口包括脉冲同步电路，用于接收与源时钟域同步的脉冲，并且响应于将忙信号输出到源时钟域并输出与所述目的地时钟域同步的脉冲; 输入寄存器，用于在所述忙信号不活动的情况下响应于所述源时钟的转变来锁存来自所述源时钟域的数据，并且在所述忙信号有效的情况下防止所述数据被锁存，以便先前不会损坏锁定数据; 以及输出寄存器，用于从所述脉冲同步电路接收所述脉冲，并且响应于在所述目的地时钟的转变时从所述输入寄存器锁存所述脉冲。

78. 发明申请

US20140052951A1 Method and Apparatus for Transferring Data from a First Domain to a Second Domain 有权
标题翻译：将数据从第一域传输到第二域的方法和装置
公开(公告)号：US20140052951A1
公开(公告)日：2014-02-20
申请号：US13763960
申请日：2013-02-11
申请人： RENESAS MOBILE CORPORATION
发明人： Ari Tapani KULMALA , Jaakko Illmari Sertamo
IPC分类号： G06F3/06
CPC分类号： G06F3/0656 , G06F3/0644 , G06F5/10 , G06F13/124 , G06F13/1689 , G06F2205/102
摘要： Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer having been made available. The token is passed to the first domain and synchronised with the first clock signal. The writing of data to the memory buffer is controlled based on a comparison between the synchronised token and a previously received token.
摘要翻译：数据从第一域写入第二域中的FIFO存储缓冲区。第一个域使用第一个时钟信号，第二个域使用第二个时钟信号，而存储器缓冲器使用与数据一起传送的第一个时钟信号。使用第二时钟信号从存储器缓冲器读取数据。读取指针被调整并与传递的第一时钟信号同步。基于读取指针，使用传送的第一时钟信号生成令牌。令牌表示存储器缓冲器已经可用的容量。令牌被传递到第一个域并与第一个时钟信号同步。基于同步令牌和先前接收到的令牌之间的比较来控制对存储器缓冲器的数据写入。

79. 发明申请

US20130039133A1 Data Storage for Voltage Domain Crossings 有权
标题翻译：电压域交叉口的数据存储
公开(公告)号：US20130039133A1
公开(公告)日：2013-02-14
申请号：US13208450
申请日：2011-08-12
申请人： Christopher Edward Koob , Jen Tsung Lin , Manojkumar Pyla , Martin Saint-Laurent
发明人： Christopher Edward Koob , Jen Tsung Lin , Manojkumar Pyla , Martin Saint-Laurent
IPC分类号： G11C5/14
CPC分类号： G06F5/06 , G06F5/10 , G06F5/14 , G06F2205/102 , G11C5/145
摘要： According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.
摘要翻译：根据实施例，一种装置包括数据存储装置。要存储在数据存储设备中的数据在被存储在数据存储设备中之前从第一电压域电平移位到第二电压域。数据存储设备由第二电压域供电。该装置还包括由第二电压域供电并且响应于数据存储装置输出的数据的电路。

80. 发明申请

US20130013950A1 CLOCK DOMAIN CROSSING INTERFACE 有权
标题翻译：时钟交叉界面
公开(公告)号：US20130013950A1
公开(公告)日：2013-01-10
申请号：US13176160
申请日：2011-07-05
申请人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
发明人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F5/10 , G06F2205/102 , H04L7/005 , H04L7/02
摘要： A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.
摘要翻译：在SoC设备的时钟域之间提供灵活且可扩展的双向CDC接口。接口包括脉冲同步电路，用于接收与源时钟域同步的脉冲，并且响应于将忙信号输出到源时钟域并输出与所述目的地时钟域同步的脉冲; 输入寄存器，用于在所述忙信号不活动的情况下响应于所述源时钟的转变来锁存来自所述源时钟域的数据，并且在所述忙信号有效的情况下防止所述数据被锁存，以便先前不会损坏锁定数据; 以及输出寄存器，用于从所述脉冲同步电路接收所述脉冲，并且响应于在所述目的地时钟的转变时从所述输入寄存器锁存所述脉冲。

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