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71. 发明专利

JP2009054709A Dust core and manufacturing method therefor 审中-公开
标题翻译：其制造方法及其制造方法
公开(公告)号：JP2009054709A
公开(公告)日：2009-03-12
申请号：JP2007218589
申请日：2007-08-24
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： EDO MASAHARU , HIROSE TAKAYUKI , SATO HIROSHI
IPC分类号： H01F41/02 , B22F1/00 , B22F1/02 , B22F3/00 , B22F3/02 , C22C19/03 , H01F1/20 , H01F1/24 , H01F1/33
摘要： PROBLEM TO BE SOLVED: To form a dust core having high magnetic permeability and proper frequency characteristics which is suitable for a high-frequency transformer, reactor, inductor, and the like. SOLUTION: The manufacturing method of the dust core is constituted in that compound magnetic particles obtained, by mixing soft magnetic metal particles of 1 to 10 μm in average particle size and nanometal magnetic particles of 5 to 100 nm in average particle size with each other are subjected to powder compression molding. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：形成适用于高频变压器，电抗器，电感器等的具有高磁导率和适当频率特性的防尘芯。解决方案：粉尘芯的制造方法是通过将平均粒径为1〜10μm的软磁性金属粒子和平均粒径为5〜100nm的纳米级磁性粒子混合而得到的复合磁性粒子与彼此进行粉末压缩成型。版权所有（C）2009，JPO＆INPIT

72. 发明专利

JP2009044814A Synchronous rectifying dc/dc converter 审中-公开
标题翻译：同步整流DC / DC转换器
公开(公告)号：JP2009044814A
公开(公告)日：2009-02-26
申请号：JP2007205177
申请日：2007-08-07
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： KAWASHIMA TETSUYA , YAMADA KOHEI , SUGAWARA SATOSHI
IPC分类号： H02M3/155
摘要： PROBLEM TO BE SOLVED: To provide a synchronous rectifying DC/DC converter which can set the dead time which is of optimal length, without having to depend on the input power supply voltage.
SOLUTION: In the synchronous rectifying DC/DC converter which obtains an output voltage (Vout) of a desired magnitude by converting a DC input voltage (PVDD), the converter comprises a switching element Q1, which performs on/off-operations; a rectifying element Q2 which performs on/off-operations at timing which is complementary to the switching element Q1; a control circuit 10, which controls the switching element Q1 and the rectifying element Q2 by using a dead time to turning them off; a level shift circuit 5, which converts a voltage level of a control signal outputted to the switching element Q1 from the control circuit 10; and a level shift circuit 6, which converts the voltage level of a control signal outputted to the rectifying element Q2 from the control circuit 10.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以设置最佳长度的死区时间的同步整流DC / DC转换器，而不必依赖于输入电源电压。解决方案：在通过转换DC输入电压（PVDD）获得期望幅度的输出电压（Vout）的同步整流DC / DC转换器中，转换器包括执行开/关操作的开关元件Q1 ; 整流元件Q2，在与开关元件Q1互补的定时进行接通/断开动作; 控制电路10，通过使用死区时间来切断开关元件Q1和整流元件Q2; 电平移位电路5，其从控制电路10转换输出到开关元件Q1的控制信号的电压电平; 以及电平移位电路6，其从控制电路10转换输出到整流元件Q2的控制信号的电压电平。版权所有（C）2009，JPO＆INPIT

73. 发明专利

JP2009043952A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009043952A
公开(公告)日：2009-02-26
申请号：JP2007207561
申请日：2007-08-09
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： KAWASHIMA TOMOYUKI
IPC分类号： H01L21/336 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of preventing a film thickness detecting function from being damaged even when the width of an initial insulating film is narrowed and an occupancy area ratio is lowered while sectioning unit cells by the initial insulating film, shortening the epitaxial growth time, shortening the polishing time, and increasing film thickness accuracy after polishing.
SOLUTION: The manufacturing method of the semiconductor device has a process of forming a first opening 3 so as to leave an initial oxide film 2 to be a film thickness reference in polishing at the outer peripheral part 17 of an active part inside the active part 16, filling the first opening 3 by epitaxial growth from two second openings 5-1 and 5-2 which are provided on a substrate oxide film 4 formed at the bottom part of the first opening 3 for each unit cell including the section opening of the respective unit cells, then polishing the grown film 14 with the thickness of the initial oxide film as a reference to turn it to a single crystal thin film 15, then forming a third opening 5-3 on the crystal thin film 15 so as to correspond to the section opening of the unit cell and re-filling it with an insulating film 2-1.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供能够防止薄膜厚度检测功能的半导体器件的制造方法，即使当初始绝缘膜的宽度变窄并且占据面积比降低时，切片单元电池通过初始绝缘膜，缩短外延生长时间，缩短抛光时间，并且在抛光后提高膜厚精度。解决方案：半导体器件的制造方法具有形成第一开口3的过程，以便在内部的有源部分的外周部分17处在抛光中留下初始氧化膜2作为膜厚度参考活性部分16，通过从形成在第一开口3的底部的基板氧化物膜4上的两个第二开口5-1和5-2的外延生长填充第一开口3，用于每个包括截面的单元电池，然后用初始氧化膜的厚度研磨生长的膜14作为参考，将其转变为单晶薄膜15，然后在晶体薄膜15上形成第三开口5-3，以便以对应于晶胞的截面开口并用绝缘膜2-1再填充它。版权所有（C）2009，JPO＆INPIT

74. 发明专利

JP2009038957A Switching power supply 有权
标题翻译：切换电源
公开(公告)号：JP2009038957A
公开(公告)日：2009-02-19
申请号：JP2008079789
申请日：2008-03-26
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： SHIMIZU HIDEO
IPC分类号： H02M7/12 , G05F1/10 , H02M3/155
摘要： PROBLEM TO BE SOLVED: To provide a switching power supply reducing noises and improving power factor.
SOLUTION: An error voltage Verr amplified by an amplifier 8, and an input voltage Vin, are multiplied together by a multiplier 9 to generate a first threshold value signal Vth1, which is in-phase with and similar in waveform to the input voltage Vin, and proportional in amplitude to the error voltage Verr. A second threshold value signal Vth2 is generated from the first threshold value signal Vth1 by a series circuit of a diode 14G and a resistor 14B. The power factor is increased by on/off-control of a switching element 7 via a drive circuit 13, so that a current detection signal, which is detected by a resistor 12 and corresponds to an input current, falls between the two threshold value signals Vth1 and Vth2. Since the off time is not fixed, the noise spectrum is spread and increase of the switching frequency is suppressed. Noise reduction is thus achieved.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种降低噪声并提高功率因数的开关电源。解决方案：由放大器8放大的误差电压Verr和输入电压Vin由乘法器9相乘，以产生第一阈值信号Vth1，其与输入的波形同相和相似电压Vin，并且在幅度上与误差电压Verr成正比。通过二极管14G和电阻器14B的串联电路从第一阈值信号Vth1产生第二阈值信号Vth2。功率因数通过驱动电路13对开关元件7的开/关控制而增加，使得由电阻器12检测并对应于输入电流的电流检测信号落在两个阈值信号之间 Vth1和Vth2。由于关闭时间不固定，噪声频谱扩展，并且抑制了开关频率的增加。从而实现降噪。版权所有（C）2009，JPO＆INPIT

75. 发明专利

JP2009038569A Microphone system 审中-公开
标题翻译：麦克风系统
公开(公告)号：JP2009038569A
公开(公告)日：2009-02-19
申请号：JP2007200767
申请日：2007-08-01
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： IWAMOTO MOTOMITSU
IPC分类号： H04R3/00
摘要： PROBLEM TO BE SOLVED: To provide a microphone system having improved resistance with respect to electromagnetic noise.
SOLUTION: The microphone system 1 has an amplifier 3, incorporating a condenser microphone 4 whose electrostatic capacity changes according to sound pressure to be applied as an impedance element for changing the gain; an AC signal source 2 for inputting an AC signal at a prescribed frequency to the amplifier 3; and a demodulation circuit 5 for demodulating the output signal of the amplifier 3. The condenser microphone 4 is provided so that the gain is changed by an impedance change, based on a change in the electrostatic capacity, thereby obtaining a signal, where the AC signal is subjected to amplitude modulation by a sound signal based on the sound pressure as the output signal of the amplifier 3.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有相对于电磁噪声的改进电阻的麦克风系统。麦克风系统1具有放大器3，其包括电容式麦克风4，其静电容量根据声压而变化，作为用于改变增益的阻抗元件; 用于向放大器3输入规定频率的AC信号的AC信号源2; 以及解调电路5，用于解调放大器3的输出信号。电容式传声器4被设置成基于静电电容的变化而通过阻抗变化改变增益，从而获得信号，其中AC信号通过基于声压的声音信号进行幅度调制作为放大器3的输出信号。版权所有（C）2009，JPO＆INPIT

76. 发明专利

JP2009022125A Method of controlling switching power supply 审中-公开
标题翻译：控制切换电源的方法
公开(公告)号：JP2009022125A
公开(公告)日：2009-01-29
申请号：JP2007183892
申请日：2007-07-13
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： NISHIKAWA YUKIHIRO
IPC分类号： H02M3/155
摘要： PROBLEM TO BE SOLVED: To enable suppressing variation in output voltage without causing scale-up or cost increase of a switching power supply unit.
SOLUTION: The switching power supply unit is provided with an error amplifier 7 for amplifying an error between a DC output and a first reference voltage, and a carrier signal generator 8, wherein a comparator 9 turns on/off the switching elements 1, 2 on the basis of a result of comparison between the output of the error amplifier and the carrier signal to obtain a constant DC output. The switching power supply unit is provided with a comparator 15 and the switching elements are forcibly switched on at a timing at which the output of the error amplifier 7 exceeds a second reference voltage Vt so that a loss time in switching is eliminated and the variation in output voltage is suppressed.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了能够抑制开关电源单元的放大或成本增加的输出电压的变化。解决方案：开关电源单元设置有用于放大DC输出和第一参考电压之间的误差的误差放大器7和载波信号发生器8，其中比较器9使开关元件1导通/截止，2基于误差放大器的输出与载波信号的比较结果，以获得恒定的DC输出。开关电源单元设置有比较器15，并且在误差放大器7的输出超过第二参考电压Vt的定时将开关元件强制接通，从而消除了开关中的损耗时间，输出电压被抑制。版权所有（C）2009，JPO＆INPIT

77. 发明专利

JP2009019973A Semiconductor pressure sensor 有权
标题翻译：半导体压力传感器
公开(公告)号：JP2009019973A
公开(公告)日：2009-01-29
申请号：JP2007182299
申请日：2007-07-11
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： KATO HIROBUMI , SHINODA SHIGERU , NISHIKAWA MUTSUO , KAMIYANAGI KATSUMICHI
IPC分类号： G01L9/00 , H01L29/84
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor pressure sensor which does not introduce temperature hysteresis between ambient temperature and a sensor output even when a chip size is reduced while a circuit pattern of the same diaphragm diameter and the same design rule is maintained.
SOLUTION: The semiconductor pressure sensor includes: a sensor area 11a which has a thin-film diaphragm 12a formed by a recessed part provided at the central part of one surface of a p-type semiconductor substrate 13a and includes a pressure gauge 14a which is a p-type area formed in an N-type island area formed on the other surface facing the diaphragm 12a; and a circuit area 10a which is formed in the semiconductor substrate 13a outside the sensor area 11a and includes a circuit for amplifying an electric signal obtained by converting external pressure received by the diaphragm. The circuit area 10a extends within the other surface which is outside the sensor area and faces the diaphragm 12a.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供即使当芯片尺寸减小时也不会在环境温度和传感器输出之间引入温度滞后的半导体压力传感器，而具有相同膜片直径和相同设计规则的电路图案被保持。解决方案：半导体压力传感器包括：传感器区域11a，其具有由设置在p型半导体衬底13a的一个表面的中心部分的凹部形成的薄膜隔膜12a，并且包括压力计14a 其是形成在面向隔膜12a的另一表面上形成的N型岛区域中的p型区域; 以及电路区域10a，其形成在传感器区域11a外部的半导体衬底13a中，并且包括用于放大通过转换由膜片接收的外部压力而获得的电信号的电路。电路区域10a在传感器区域之外的另一表面内延伸并且面向隔膜12a。版权所有（C）2009，JPO＆INPIT

78. 发明专利

JP2008311543A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2008311543A
公开(公告)日：2008-12-25
申请号：JP2007159645
申请日：2007-06-18
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： URANO YUICHI
IPC分类号： H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device that can prevent peeling of a tungsten film in forming the tungsten film.
SOLUTION: On a semiconductor substrate 1 with an aluminum wiring 2 formed, a first P-TEOS film 3, an O3-NSG film 4, a second P-TEOS film 5, an organic SOG film 6, a third P-TEOS film 7 after etching-back are sequentially stacked on the preceding film. Further, on a stacked interlayer insulating film on the aluminum wiring 2, a Via contact 8, a TiN film 9, and then a tungsten film 11 are formed in the next step after annealing 10 of the TiN film 9. Annealing of the TiN film 9 can prevent peeling of the tungsten film 11.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止在形成钨膜时钨膜的剥离的半导体器件的制造方法。解决方案：在形成有铝布线2的半导体基板1上，第一P-TEOS膜3，O3-NSG膜4，第二P-TEOS膜5，有机SOG膜6，第三P- 蚀刻后的TEOS膜7依次层叠在前述膜上。此外，在铝布线2上的堆叠层间绝缘膜上，在退火10 TiN膜9之后，在下一步骤中形成通孔接触8，TiN膜9，然后形成钨膜11。退火TiN膜 9可以防止钨膜11的剥离。版权所有（C）2009，JPO＆INPIT

79. 发明专利

JP2008311540A Vertical mos semiconductor device and method of manufacturing the same 审中-公开
标题翻译：垂直MOS半导体器件及其制造方法
公开(公告)号：JP2008311540A
公开(公告)日：2008-12-25
申请号：JP2007159642
申请日：2007-06-18
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： YOSHIKAWA ISAO
IPC分类号： H01L29/739 , H01L21/265 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a vertical MOS semiconductor device having a top gate structure which can enhance latch-up resistance quantity without increasing on voltage, and to provide a method of manufacturing the same.
SOLUTION: In the vertical MOS semiconductor device having a top gate structure, the structure is configured in such a way that the body region of the other conductive type is disposed closer to the second opening section than to the end part of the gate oxide film while assuring the channel formation directly under a gate insulating film at a cathode layer.
COPYRIGHT: (C)2009,JPO&INPIT

80. 发明专利

JP2008310849A Protective film forming method and magnetic recording medium including protective film 审中-公开
标题翻译：保护膜形成方法和磁记录介质，包括保护膜
公开(公告)号：JP2008310849A
公开(公告)日：2008-12-25
申请号：JP2007155332
申请日：2007-06-12
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： RI ZUKYO , MIYASATO MAKI , ONIZUKA TAKESHI , ISOZAKI MAKOTO , KURIHARA MASARU
IPC分类号： G11B5/84 , G11B5/72
CPC分类号： G11B5/8408 , C23C16/26 , C23C16/5096
摘要： PROBLEM TO BE SOLVED: To provide a magnetic recording medium having superior electromagnetic conversion characteristics and corrosion resistance and a protective film forming method capable of improving electromagnetic conversion characteristics by thinning the film without damaging a magnetic layer.
SOLUTION: In the protective film forming method forming a carbon protective film by a high frequency plasma CVD method on a disk in which at least the magnetic film is formed on a nonmagnetic substrate, a bias voltage of 0 to -200 V is applied at the initial discharge in the formation of the carbon protective film, and a voltage of -200 V or less and -500 V or more is applied at the end of the discharge. In the magnetic recording medium including at least the magnetic film and the protective film on the nonmagnetic substrate, the protective film is formed by the protective film forming method.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有优异的电磁转换特性和耐腐蚀性的磁记录介质和能够通过使薄膜变薄而不损坏磁性层来改善电磁转换特性的保护膜形成方法。解决方案：在通过高频等离子体CVD方法在至少在非磁性基板上形成磁性膜的盘上形成碳保护膜的保护膜形成方法中，0至-200V的偏置电压为在初始放电时施加碳保护膜的形成，并且在放电结束时施加-200V以下且-500V以上的电压。在至少包括非磁性基板上的磁性膜和保护膜的磁记录介质中，通过保护膜形成方法形成保护膜。版权所有（C）2009，JPO＆INPIT

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