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71. 发明专利

DE4311966A1 未知
公开(公告)号：DE4311966A1
公开(公告)日：1993-10-21
申请号：DE4311966
申请日：1993-04-10
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： SWANSON ERIC J , THOMPSON CHARLES D
IPC分类号： H03M1/08 , H03M3/02 , H03M1/06 , H03M3/00 , H03M5/02
摘要： The output gates of a delta-sigma modulator can generate i(t) transient signal in the power supply lines of a delta-sigma modulator. These i(t) spikes, which would otherwise produce non-linearities which can be coupled into the frequency band of interest of the modulator, are made to be linear by using return-to-zero data encoding and by providing multi-bit outputs to the delta-sigma modulator in which the output states all have equal numbers of logic ones at the output lines for each of the output states.

72. 发明专利

DE4202180C2 未知
公开(公告)号：DE4202180C2
公开(公告)日：1993-06-17
申请号：DE4202180
申请日：1992-01-28
申请人： CRYSTAL SEMICONDUCTOR CORP., AUSTIN, TEX., US
发明人： SOOCH, NAVDEEP SINGH, AUSTIN, TEX., US
IPC分类号： H03M1/06 , H02H3/24 , H03M1/00 , H03M1/66
摘要： A digital-to-analog converter for operating in a low power condition includes a delta-sigma modulator (10) for converting an n-bit digital input signal to an m-bit digital output signal. The output signal is filtered with a switched-capacitor filter (12) and an active RC low-pass filter (18). A low power supply detect circuit receives two power supply input voltages, the low and the high power supplies, and outputs a control signal on a line (38) indicating a low power supply condition. The digital-to-analog converter includes an output stage (26) with the analog output thereof being connected to an analog output terminal (30). A switch (28) is provided for connecting the output stage to the analog output terminal (30) in normal operating mode. In a low power mode, the low power detect circuit (20) generates a control signal on line (38) in response to the power supply voltage falling below a predetermined threshold. The switch (28) is opened and a shunt switch (32) provides a squelch operation by being configured in a closed configuration during a low power condition. Alternately, the output stage (26) can be powered down in the low power condition.

73. 发明专利

GB2261561A A FOURTH ORDER DIGITAL DELTA-SIGMA MODULATOR 未知
公开(公告)号：GB2261561A
公开(公告)日：1993-05-19
申请号：GB9217800
申请日：1992-08-21
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： DUFFY MICHAEL J , SOOCH NAVDEEP SINGH
IPC分类号： H03M3/02 , H03M7/32
摘要： A delta-sigma modulator for a digital-to-analog converter includes a single adder (60) that has one input thereof multiplexed by multiplexer (62). Four shift registers (64), (66), (68) and (70) are connected in a serial fashion such that the data output by the adder (60) is input to the shift register (64) and the other input of adder (60) is connected to the output of register (70). In operation, the multiplexer (62) first selects the input data for input to the one input of adder (60) and selects the output of register (70) for the other input. This represents the first stage of integration wherein the accumulated value from a previous cycle is added to the present data. The output of the first stage of integration will be cycled through the registers for each overall cycle of the delta-sigma modulator. In the second stage of integration on the next clock cycle of the 4x clock, the multiplexer (62) selects the output of the register (68) for adding to the output of the register (70). This represents the operation of the second stage of integration. The output of register (64) represents the output of each stage of integration after the accumulation step, which is then input to one of four shift left registers (82)-(88), which performs a gain scaling function. An overflow condition is also accommodated with an exclusive-OR gate (78).

74. 发明专利

DE4237875A1 未知
公开(公告)号：DE4237875A1
公开(公告)日：1993-05-19
申请号：DE4237875
申请日：1992-11-10
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： DUFFY MICHAEL J , SOOCH NAVDEEP SINGH
IPC分类号： H03M3/02 , H03M7/32
摘要： A delta-sigma modulator for a digital-to-analog converter includes a single adder (60) that has one input thereof multiplexed by multiplexer (62). Four shift registers (64), (66), (68) and (70) are connected in a serial fashion such that the data output by the adder (60) is input to the shift register (64) and the other input of adder (60) is connected to the output of register (70). In operation, the multiplexer (62) first selects the input data for input to the one input of adder (60) and selects the output of register (70) for the other input. This represents the first stage of integration wherein the accumulated value from a previous cycle is added to the present data. The output of the first stage of integration will be cycled through the registers for each overall cycle of the delta-sigma modulator. In the second stage of integration on the next clock cycle of the 4x clock, the multiplexer (62) selects the output of the register (68) for adding to the output of the register (70). This represents the operation of the second stage of integration. The output of register (64) represents the output of each stage of integration after the accumulation step, which is then input to one of four shift left registers (82)-(88), which performs a gain scaling function. An overflow condition is also accommodated with an exclusive-OR gate (78).

75. 发明专利

GB9305126D0 METHOD AND APPARATUS FOR CALIBRATING A MULTI-BIT DELTA-SIGMA MODULATOR 未知
公开(公告)号：GB9305126D0
公开(公告)日：1993-04-28
申请号：GB9305126
申请日：1993-03-12
申请人： CRYSTAL SEMICONDUCTOR CORP
IPC分类号： H03M1/10 , H03M3/00 , H03M3/04
摘要： A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient delta . The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The delta coefficient is stored in a block (16) and is generated during a calibration cycle by a delta processor (39). The delta processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the delta coefficient is frozen and the calibration multiplexer (10) selects the analog input.

76. 发明专利

GB9305089D0 DELTA-SIGMA MODULATOR FOR AN ANALOG-TO-DIGITAL CONVERTER WITH LOW THERMAL NOISE PERFORMANCE 未知
公开(公告)号：GB9305089D0
公开(公告)日：1993-04-28
申请号：GB9305089
申请日：1993-03-12
申请人： CRYSTAL SEMICONDUCTOR CORP
IPC分类号： H03M1/08 , H03M3/00 , H03M3/02
摘要： An analog-to-digital converter includes a two-bit delta-sigma modulator. The delta-sigma modulator is comprised of a first stage integrator (10) that feeds a noise shaping circuit (18). The output of the noise shaping circuit (18) is input to a two-threshold imbedded ADC (20) to provide the two-bit output. This output of the imbedded ADC (20) is input to a digital filter (22) to provide the filtered digital output, this filtering high-frequency noise. The output of the imbedded ADC (20) is also fed back through a three-level DAC (24) to a summing junction on the input of the integrator (10). The three-level DAC 24 has three states that are output with one state being a "do nothing" state. The thermal noise performance of the delta-sigma modulator as a function of the quantizer threshold voltages is first simulated and then the value of the quantizer thresholds selected to provide optimum signal-to-thermal noise performance.

77. 发明专利

GB9303715D0 RESYNCHRONIZATION OF A SYNCHRONOUS SERIAL INTERFACE 未知
公开(公告)号：GB9303715D0
公开(公告)日：1993-04-14
申请号：GB9303715
申请日：1993-02-24
申请人： CRYSTAL SEMICONDUCTOR CORP
IPC分类号： H04L7/00 , G06F13/42 , H04L7/08 , H04L7/10 , H04L25/40 , H04L25/45 , H04L29/08

78. 发明专利

GB2256551A SWITCHED-CAPACITOR INTEGRATOR WITH CHOPPER STABILIZATION PERFORMED AT THE SAMPLING RATE 未知
公开(公告)号：GB2256551A
公开(公告)日：1992-12-09
申请号：GB9206964
申请日：1992-03-31
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： KERTH DONALD ALLAN
IPC分类号： H03F3/38 , G06G7/186 , H03H19/00 , H03M3/02

79. 发明专利

GB9217775D0 OFFSET CALIBRATION OF A DAC USING A CALIBRATED ADC 未知
公开(公告)号：GB9217775D0
公开(公告)日：1992-10-07
申请号：GB9217775
申请日：1992-08-21
申请人： CRYSTAL SEMICONDUCTOR CORP
IPC分类号： H03M1/10 , H03H17/00 , H03H17/02 , H03M3/02
摘要： A calibrated digital-to-analog converter (DAC) is provided that includes a DAC having an interpolation circuit (40) and delta-sigma converter (44). The output of the delta-sigma converter (44) is input to a one-bit DAC (48) and the output thereof filtered by an analog low pass filter section (50). During a calibration procedure, a calibrated analog-to-digital converter (ADC) (22) is utilized that is operable to receive the analog output of the DAC with a "0" value input thereto through a multiplexer (58). The output of the ADC (22) represents the inherent error in the delta-sigma converter (44) and the analog filter section (50). This is stored in a register (62). In a second step of the operation, the contents of the register (62) are input through the interpolation circuit for interpolation thereof and storage in an offset register/latch circuit (56). The contents of the latch (56) are input to a summing junction (54) which, in normal operation, are summed with the output of the interpolation circuit (40) for input to the delta-sigma converter (44). By disposing the summing junction (54) between the interpolation circuit (40) and the delta-sigma modulator (44), the bit load on the input of the interpolation (40) can be reduced. By utilizing the interpolation circuit (40) in the calibration procedure, the gain thereof can be compensated for in the value stored in the register/latch (56).

80. 发明专利

GB2253754A HIGH ORDER SWITCHED-CAPACITOR FILTER WITH DAC INPUT. 未知
公开(公告)号：GB2253754A
公开(公告)日：1992-09-16
申请号：GB9200510
申请日：1992-01-10
申请人： CRYSTAL SEMICONDUCTOR CORP
发明人： SOOCH NAVDEEP SINGH
IPC分类号： H03H19/00 , H03M1/66 , H03M3/02 , H03M7/00
摘要： A digital-to-analog converter includes a delta-sigma modulator (10) that receives a digital input and converts it to a one-bit digital output stream. A fourth order switched-capacitor filter (12) receives the one-bit digital stream and converts it to an analog value in the sampled data domain. This is input to a switched-capacitor/continuous time buffer (14) which is then filtered by an active low pass filter (18) to provide an analog output. A one-bit DAC 20 is provided for converting the one-bit digital stream to an analog value. The one-bit DAC 20 is integral with the first stage of integration and is summed by a summing junction 22 with the output of the fourth stage of integration 38. In this manner, the first stage of integration 24 is operable to influence or reduce the noise output by the fourth stage of integration (38), thus resulting in a low noise, high order switched-capacitor filter.

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