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71. 发明授权

US06620713B2 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication 失效
标题翻译：栅电极和高k电介质层的界面层及其制造方法
公开(公告)号：US06620713B2
公开(公告)日：2003-09-16
申请号：US10038410
申请日：2002-01-02
申请人： Reza Arghavani , Robert Chau , Mark Doczy , Brian Roberds
发明人： Reza Arghavani , Robert Chau , Mark Doczy , Brian Roberds
IPC分类号： H01L213205
CPC分类号： H01L21/28176 , H01L21/28035 , H01L21/28185 , H01L21/28194 , H01L21/31683 , H01L29/4925 , H01L29/517
摘要： Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.
摘要翻译：制造半导体器件的方法半导体器件包括衬底，形成在衬底上的高k栅介质层和沉积在高k栅介质层上的无氢栅电极，其中无氢栅电极是导电的。该方法包括在衬底上沉积高k栅极电介质层，在栅极电介质层上溅射栅电极并处理栅电极使得栅电极是导电的。

72. 发明授权

US06261925B1 N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress 失效
标题翻译： N2O氮化氧化物沟槽侧壁，以防止硼扩散并减少应力
公开(公告)号：US06261925B1
公开(公告)日：2001-07-17
申请号：US09075490
申请日：1998-05-08
申请人： Reza Arghavani , Robert S. Chau , Simon Yang , John Graham
发明人： Reza Arghavani , Robert S. Chau , Simon Yang , John Graham
IPC分类号： H01L21762
CPC分类号： H01L21/31053 , H01L21/76235
摘要： A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.
摘要翻译：描述在半导体衬底中形成隔离结构的方法。首先将沟槽蚀刻到半导体衬底中。然后用沟槽形成第一氧化物层。对第一氧化物层进行氮氧化物气氛环境的退火处理，以在第一氧化物层上形成氧氮化物表面，在第一氧化物层和半导体衬底之间形成氮氧化硅界面。然后将第二氧化物层沉积在第一氧化物层的氧化氮化物表面上。本发明的方法和隔离结构防止掺杂剂扩散，减小沟槽应力，允许薄栅极氧化物的更均匀生长，并允许使用更薄的栅极氧化物。

73. 发明授权

US6087236A Integrated circuit with multiple gate dielectric structures 有权
公开(公告)号：US6087236A
公开(公告)日：2000-07-11
申请号：US198831
申请日：1998-11-24
申请人： Robert S. Chau , Reza Arghavani , Bruce Beattie
发明人： Robert S. Chau , Reza Arghavani , Bruce Beattie
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823462
摘要： An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N.sub.2 plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions. A method of forming IGFETs with different gate dielectric thicknesses and compositions, on a single integrated circuit, includes forming a first oxynitride layer, forming a masking layer, removing a portion of the first oxynitride layer, forming an oxide layer where the oxynitride was removed, and forming a plurality of gate electrodes, a first portion of the gate electrodes overlying the first oxynitride layer.

74. 发明授权

US5827769A Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode 失效
标题翻译：通过对栅电极的侧壁氧化物进行氮化和退火来制造具有增加的热载流子电阻的晶体管的方法
公开(公告)号：US5827769A
公开(公告)日：1998-10-27
申请号：US754219
申请日：1996-11-20
申请人： Payman Aminzadeh , Reza Arghavani , Peter Moon
发明人： Payman Aminzadeh , Reza Arghavani , Peter Moon
IPC分类号： H01L21/314 , H01L21/336 , H01L29/49 , H01L21/31
CPC分类号： H01L29/6659 , H01L21/3144 , H01L29/4983 , H01L29/6656
摘要： A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.
摘要翻译：公开了一种制造具有增加的抗热载体损伤的场效应晶体管的方法。在栅电极上生长氧化物。该氧化物通过氮化和退火得到加强。在轻掺杂漏极注入之后，沉积第二侧面氧化物和共形氮化物层。然后，各向异性蚀刻共形氮化物以形成用于掩蔽高剂量漏极植入物的间隔物。已经发现用该方法制造的NMOS过渡器比传统的轻掺杂漏极工艺对热载体损伤的敏感性低40％。此外，该方法已证明比侧氧化物被氮化并再次氧化的方法更可制造。

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