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71. 发明申请

US20100169579A1 READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS 有权
标题翻译：在交易记忆（TM）系统中读取和写入监视属性
公开(公告)号：US20100169579A1
公开(公告)日：2010-07-01
申请号：US12346530
申请日：2008-12-30
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Raanan Sade , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Raanan Sade , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08 , G06F3/00
CPC分类号： G06F12/0831 , G06F12/084
摘要： A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.
摘要翻译：这里描述了用于监视硬件中的存储器访问以支持事务执行的方法和装置。属性是对数据项的监视访问，而不考虑物理存储结构粒度的检测，而是确保至少在数据项粒度处进行监视。作为示例，将属性添加到高速缓存的状态位以启用新的高速缓存一致性状态。在可被选择性地确定的对数据项的监视的存储器访问之后，与数据项相关联的一致性状态被更新为监视状态。结果，通过请求类型和数据项的监视的一致性状态的组合来检测对数据项的无效请求。

72. 发明申请

US20100169382A1 METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE 有权
标题翻译：用于在硬件中保存损失元数据的地形空间
公开(公告)号：US20100169382A1
公开(公告)日：2010-07-01
申请号：US12346500
申请日：2008-12-30
申请人： Gad Sheaffer , Shlomo Raikia , Vadim Bassia , Raanan Sade , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikia , Vadim Bassia , Raanan Sade , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/02 , G06F17/30
CPC分类号： G06F12/0615 , G06F9/467 , G06F12/0842 , G06F12/1027
摘要： A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.
摘要翻译：这里描述用于保存有损元数据的形而上学地址空间的方法和装置。遇到引用数据项的数据地址的显式或隐式元数据访问操作。硬件将数据地址修改为包括形而上学扩展的元数据地址。形而上学扩展覆盖了数据地址空间上的一个或多个形而上学地址空间。使用包括形而上学扩展的元数据地址的一部分来搜索保存数据项的高速缓冲存储器的标签阵列。因此，元数据访问操作仅基于元数据地址扩展名来命中高速缓存的元数据条目。然而，随着元数据被保存在高速缓存中，元数据可能与高速缓存中的空间的数据竞争。

73. 发明申请

US20080133842A1 Protected cache architecture and secure programming paradigm to protect applications 有权
标题翻译：保护缓存架构和安全编程范例来保护应用程序
公开(公告)号：US20080133842A1
公开(公告)日：2008-06-05
申请号：US11998902
申请日：2007-12-03
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/1491 , G06F21/10
摘要： Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。描述和要求保护其他实施例。

74. 发明授权

US6105124A Method and apparatus for merging binary translated basic blocks of instructions 失效
标题翻译：用于合并二进制转换的基本指令块的方法和装置
公开(公告)号：US6105124A
公开(公告)日：2000-08-15
申请号：US672100
申请日：1996-06-27
申请人： Yaron Farber , Gad Sheaffer , Robert Valentine
发明人： Yaron Farber , Gad Sheaffer , Robert Valentine
IPC分类号： G06F9/45 , G06F11/34 , G06F11/36 , G06F9/30
CPC分类号： G06F8/445 , G06F8/52 , G06F11/3466 , G06F2201/865 , G06F2201/88
摘要： A method for merging binary translated basic blocks of instructions. The method is for use in a computer system having in a memory a first set of instructions including blocks of instructions, and a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture. The method includes a first step of determining, by the translator, an order of execution from a first block of instructions to a second block of instructions. A second step of the method includes generating, by the translator, a hyperblock of instructions representing the first and second block of instructions translated and placed adjacent in a memory location in the order of execution.
摘要翻译：一种用于合并二进制转换的基本指令块的方法。该方法用于在存储器中具有包括指令块的第一组指令的计算机系统，以及用于将可在源指令集架构上执行的指令转换为可在目标指令集架构上执行的指令的转换器。该方法包括第一步骤，由翻译器确定从第一指令块到第二指令块的执行顺序。该方法的第二步包括由翻译器生成代表按照执行次序在存储单元中相邻的第一和第二指令块的指令的超块。

75. 发明授权

US09164923B2 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform 有权
标题翻译：动态固定异构计算平台的不同类型处理器之间共享的虚拟页面
公开(公告)号：US09164923B2
公开(公告)日：2015-10-20
申请号：US13175489
申请日：2011-07-01
申请人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
发明人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/0804 , G06F12/126 , G06F13/1663 , G06F2212/303 , G06F2212/657 , G06F2212/684
摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.
摘要翻译：计算机系统可以支持一种或多种技术来允许由非CPU设备（例如，图形处理单元，GPU）访问的存储器页的动态固定。非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。在一个实施例中，设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

76. 发明授权

US08769212B2 Memory model for hardware attributes within a transactional memory system 有权
标题翻译：事务内存系统中硬件属性的内存模型
公开(公告)号：US08769212B2
公开(公告)日：2014-07-01
申请号：US13359238
申请日：2012-01-26
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3838 , G06F11/0715 , G06F11/0724 , G06F11/073 , G06F11/0751 , G06F11/3017 , G06F11/3037 , G06F11/3089 , G06F11/3471 , G06F12/0831 , G06F12/084 , G06F2201/885
摘要： A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
摘要翻译：这里描述了一种用于提供用于硬件属性以支持事务执行的存储器模型的方法和装置。在遇到诸如加载读取监视器，写入监视器或缓冲属性的测试监视器操作的硬件属性的负载时，响应于指示硬件属性已经丢失的丢失字段而发出故障。此外，基于地址依赖性和访问类型依赖性，为属性访问操作提供依赖操作，例如阻塞和转发。因此，在存储器模型中允许和限制属性丢失和测试的不同场景。

77. 发明授权

US08627014B2 Memory model for hardware attributes within a transactional memory system 有权
公开(公告)号：US08627014B2
公开(公告)日：2014-01-07
申请号：US12346539
申请日：2008-12-30
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3838 , G06F11/0715 , G06F11/0724 , G06F11/073 , G06F11/0751 , G06F11/3017 , G06F11/3037 , G06F11/3089 , G06F11/3471 , G06F12/0831 , G06F12/084 , G06F2201/885
摘要： A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.

78. 发明授权

US08209689B2 Live lock free priority scheme for memory transactions in transactional memory 有权
标题翻译：事务内存中的内存事务的实时锁定优先级方案
公开(公告)号：US08209689B2
公开(公告)日：2012-06-26
申请号：US11854175
申请日：2007-09-12
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F9/52 , G06F13/14 , G06F12/00 , G06F7/00 , G06F13/00
CPC分类号： G06F9/524 , G06F9/466
摘要： A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
摘要翻译：这里描述了用于在事务执行期间避免实时锁定的方法和装置。计数逻辑用于跟踪每个处理元素的成功提交事务。当在多个处理元件之间的事务之间检测到数据冲突时，以较低的计数逻辑值提供给处理元件的优先级。此外，如果值相同，则具有较低识别值的处理元件被赋予优先级，即允许在其他事务被中止时继续。为了避免在具有预定的计数逻辑值（例如最大计数值）的处理元件之间的实时锁定，当一个处理元件达到预定计数值时，所有计数器都被重置。此外，当计数逻辑处于最大值时，可以提供在最大值（FMV）计数器上的故障来计数事务的中止次数。当FMV计数器处于预定数量的中止时，计数逻辑被复位以避免实时锁定。

79. 发明申请

US20120159079A1 MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM 有权
标题翻译：用于存储器系统中的硬件属性的内存模型
公开(公告)号：US20120159079A1
公开(公告)日：2012-06-21
申请号：US13359238
申请日：2012-01-26
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3838 , G06F11/0715 , G06F11/0724 , G06F11/073 , G06F11/0751 , G06F11/3017 , G06F11/3037 , G06F11/3089 , G06F11/3471 , G06F12/0831 , G06F12/084 , G06F2201/885
摘要： A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
摘要翻译：这里描述了一种用于提供用于硬件属性以支持事务执行的存储器模型的方法和装置。在遇到诸如加载读取监视器，写入监视器或缓冲属性的测试监视器操作的硬件属性的负载时，响应于指示硬件属性已经丢失的丢失字段而发出故障。此外，基于地址依赖性和访问类型依赖性，为属性访问操作提供依赖操作，例如阻塞和转发。因此，在存储器模型中允许和限制属性丢失和测试的不同场景。

80. 发明申请

US20110145530A1 LEVERAGING MEMORY ISOLATION HARDWARE TECHNOLOGY TO EFFICIENTLY DETECT RACE CONDITIONS 有权
标题翻译：利用记忆分离硬件技术有效地检测条件
公开(公告)号：US20110145530A1
公开(公告)日：2011-06-16
申请号：US12638031
申请日：2009-12-15
申请人： Martin Taillefer , Gad Sheaffer
发明人： Martin Taillefer , Gad Sheaffer
IPC分类号： G06F12/14 , G06F12/08 , G06F11/07
CPC分类号： G06F11/3648
摘要： One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread one or more software instructions to place a software lock on data. As a result of executing one or more software instructions to place a software lock on data, several additional acts are performed. In particular, the thread places a software lock on the data locking the data for at least one of exclusive writes or reads by the thread. And, at a local cache memory local to the thread, the thread enters the thread's memory isolation mode enabling local hardware buffering of memory writes and monitoring of conflicting writes or reads to or from the cache memory to detect reads or writes by non-lock respecting agents.
摘要翻译：一个实施例包括用于检测竞态条件的方法动作。该方法包括开始关键部分，在此期间应检测到冲突的读取和写入，以确定是否发生了竞争条件。这通过在线程执行一个或多个软件指令来执行以对软件锁定数据。作为执行一个或多个软件指令以对数据进行软件锁定的结果，执行几个附加动作。特别地，线程将软件锁定在锁定数据的数据上，用于线程的排他写入或读取中的至少一个。而且，在线程本地的本地高速缓存中，线程进入线程的内存隔离模式，使本地硬件缓冲内存写入并监视与高速缓冲存储器冲突的写入或读取，以通过非锁定来检测读取或写入代理商

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