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71. 发明申请

US20130195991A1 Composition for Treatment of Damaged Part 审中-公开
标题翻译：治疗损伤部位的组成
公开(公告)号：US20130195991A1
公开(公告)日：2013-08-01
申请号：US13637107
申请日：2011-03-25
申请人： Minoru Ueda , Yoichi Yamada , Katsumi Ebisawa , Akihito Yamamoto , Kiyoshi Sakai , Kohki Matsubara , Hisashi Hattori , Masahiko Sugiyama , Takanori Inoue
发明人： Minoru Ueda , Yoichi Yamada , Katsumi Ebisawa , Akihito Yamamoto , Kiyoshi Sakai , Kohki Matsubara , Hisashi Hattori , Masahiko Sugiyama , Takanori Inoue
IPC分类号： A61K35/12
CPC分类号： A61K35/12 , A61K35/28 , A61K35/30 , A61K35/32 , A61K35/545 , A61K38/18 , A61K38/1833 , A61K38/1841 , A61K38/1858 , A61K38/1866 , A61K38/30 , C12N5/0664 , A61K2300/00
摘要： The present invention provides a damaged part treatment composition for repairing a damaged part of a target tissue that includes a stem cell-conditioned medium obtained by culturing stem cells; a damaged part treatment method for repairing or restoring a damaged part of a target tissue that includes administering the damaged part treatment composition to a patient having the target tissue for the damaged part treatment composition in an amount therapeutically effective for repairing the damaged part of the target tissue; a method of treating cerebral infarction that includes administering the damaged part treatment composition to a cerebral infarct patient in an amount effective for repairing a damaged part of the brain; and a method of treating a CNS disease that includes administering, as a CNS disease treatment composition, the damaged part treatment composition to a CNS disease patient in a therapeutically effective amount.
摘要翻译：本发明提供一种用于修复目标组织的损伤部分的损伤部分处理组合物，其包括通过培养干细胞获得的干细胞条件培养基; 用于修复或恢复目标组织的损伤部分的损坏部分处理方法，包括将损伤的部分处理组合物施用于具有损伤部分处理组合物的目标组织的患者，其量以治疗有效的量修复靶的损伤部分组织; 一种治疗脑梗死的方法，其包括以有效修复脑损伤部分的量将损伤的部分治疗组合物给予脑梗死患者; 以及治疗CNS疾病的方法，其包括以治疗有效量向CNS疾病患者施用所述损伤的部分治疗组合物作为CNS疾病治疗组合物。

72. 发明授权

US08110865B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08110865B2
公开(公告)日：2012-02-07
申请号：US12888140
申请日：2010-09-22
申请人： Masayuki Tanaka , Daisuke Nishida , Ryota Fujitsuka , Katsuyuki Sekine , Akihito Yamamoto , Katsuaki Natori , Yoshio Ozawa
发明人： Masayuki Tanaka , Daisuke Nishida , Ryota Fujitsuka , Katsuyuki Sekine , Akihito Yamamoto , Katsuaki Natori , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7883
摘要： A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储层，形成在电荷存储层上的第二绝缘膜，以及形成在第二绝缘膜上的控制电极，所述第二绝缘膜包括下氮化硅膜，形成在所述下氮化硅膜上的下氧化硅膜，形成在所述下氧化硅膜上并含有金属元素的中间绝缘膜，所述中间绝缘膜具有相对电介质大于7的常数，形成在中间绝缘膜上的上部氧化硅膜和形成在上部氧化硅膜上的上部氮化硅膜。

73. 发明授权

US08008732B2 Semiconductor memory and method of manufacturing the same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US08008732B2
公开(公告)日：2011-08-30
申请号：US11858731
申请日：2007-09-20
申请人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
发明人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L27/115
CPC分类号： H01L27/249 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L29/513 , H01L29/518 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
摘要翻译：半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

74. 发明申请

US20100136780A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100136780A1
公开(公告)日：2010-06-03
申请号：US12686005
申请日：2010-01-12
申请人： Katsuaki Natori , Masayuki Tanaka , Akihito Yamamoto , Katsuyuki Sekine , Ryota Fujitsuka , Daisuke Nishida , Yoshio Ozawa
发明人： Katsuaki Natori , Masayuki Tanaka , Akihito Yamamoto , Katsuyuki Sekine , Ryota Fujitsuka , Daisuke Nishida , Yoshio Ozawa
IPC分类号： H01L21/28
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.
摘要翻译：一种制造半导体器件的方法，包括形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储层，形成在电荷存储层上的第二绝缘膜，以及形成在第二绝缘膜上的控制电极其中，形成所述第二绝缘膜包括使用不含氯的源气体形成含硅的绝缘膜，以及在含有硅的绝缘膜上形成含有氧和金属元素的绝缘膜。

75. 发明授权

US07612404B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07612404B2
公开(公告)日：2009-11-03
申请号：US11783933
申请日：2007-04-13
申请人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujisuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
发明人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujisuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/513
摘要： A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.
摘要翻译：半导体器件包括半导体衬底，隔离绝缘膜，非易失性存储单元，每个单元包括隧道绝缘膜，FG电极，CG电极，CG和FG电极之间的电极间绝缘膜，并且包括第一绝缘膜和第二绝缘膜在第一绝缘膜上并且具有比第一绝缘膜高的介电常数，电极间绝缘膜设置在浮栅电极的侧壁上，在电池的沟道宽度方向的横截面图中，绝缘电极的绝缘层的厚度膜从侧壁的上部向侧壁的下部增加，FG电极的上角上的第二绝缘膜的厚度比侧壁的其他部分上的第二绝缘膜的厚度厚在通道宽度方向的横截面视图中。

76. 发明申请

US20080073635A1 Semiconductor Memory and Method of Manufacturing the Same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20080073635A1
公开(公告)日：2008-03-27
申请号：US11858731
申请日：2007-09-20
申请人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
发明人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/249 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L29/513 , H01L29/518 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
摘要翻译：半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

77. 发明申请

US20080054341A1 Semiconductor memory device and method for manufacturing same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080054341A1
公开(公告)日：2008-03-06
申请号：US11892282
申请日：2007-08-21
申请人： Katsuaki Natori , Masayuki Tanaka , Akihito Yamamoto
发明人： Katsuaki Natori , Masayuki Tanaka , Akihito Yamamoto
IPC分类号： H01L29/788 , H01L21/3205
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.
摘要翻译：半导体存储器件包括多个存储晶体管。每个存储晶体管具有：浮栅电极; 电极间绝缘膜; 和控制栅电极。浮栅电极在沿着位线方向的截面中包括第一导电膜，跨越第一导电膜的彼此相对的第一侧壁绝缘膜和设置在第一侧壁绝缘膜上的第二导电膜和第一导电膜。电极间绝缘膜设置在第二导电膜上。控制栅电极包括设置在电极间绝缘膜上的第三导电膜和设置在第三导电膜上的第四导电膜。

78. 发明申请

US20070241388A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20070241388A1
公开(公告)日：2007-10-18
申请号：US11783933
申请日：2007-04-13
申请人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
发明人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/513
摘要： A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.
摘要翻译：半导体器件包括半导体衬底，隔离绝缘膜，非易失性存储单元，每个单元包括隧道绝缘膜，FG电极，CG电极，CG和FG电极之间的电极间绝缘膜，并且包括第一绝缘膜和第二绝缘膜在第一绝缘膜上并且具有比第一绝缘膜高的介电常数，电极间绝缘膜设置在浮栅电极的侧壁上，在电池的沟道宽度方向的横截面图中，绝缘电极的绝缘层的厚度膜从侧壁的上部向侧壁的下部增加，FG电极的上角上的第二绝缘膜的厚度比侧壁的其他部分上的第二绝缘膜的厚度厚在通道宽度方向的横截面视图中。

79. 发明申请

US20070137567A1 Apparatus for manufacturing a semiconductor device 审中-公开
标题翻译：用于制造半导体器件的装置
公开(公告)号：US20070137567A1
公开(公告)日：2007-06-21
申请号：US11706951
申请日：2007-02-16
申请人： Takashi Shimizu , Akihito Yamamoto
发明人： Takashi Shimizu , Akihito Yamamoto
IPC分类号： C23C16/00
CPC分类号： C23C16/455 , C23C16/4405 , C23C16/52
摘要： An apparatus for manufacturing a semiconductor device, including a process chamber which holds a substrate to be subjected to a prescribed process, a gas inlet pipe which introduces a process gas into the process chamber, a gas outlet pipe which discharges the gas from the process chamber to outside the process chamber, component-measuring devices which measure components of the gas in the process chamber or at least two different gases, concentration-measuring devices which measure concentration of each component of the gas in the process chamber, or the concentration of each component of at least two different gases, and a control device which adjusts the components of the process gas, the concentration of each component of the process gas and an atmosphere in the process chamber, on the basis of values measured by the component-measuring device and concentration-measuring device.
摘要翻译：一种用于制造半导体器件的装置，包括：保持要进行规定处理的基板的处理室;将处理气体引入处理室的气体导入管，从处理室排出气体的气体出口管在处理室外部，测量处理室中的气体成分或至少两种不同气体的组分测量装置，测量处理室中气体的每个组分的浓度的浓度测量装置，或每个至少两种不同气体的组分，以及控制装置，其基于由部件测量装置测量的值来调节处理气体的组分，处理气体的每个组分的浓度和处理室中的气氛和浓度测定装置。

80. 发明申请

US20050284575A1 Processing system and operating method of processing system 审中-公开
标题翻译：处理系统和处理系统的操作方法
公开(公告)号：US20050284575A1
公开(公告)日：2005-12-29
申请号：US11196398
申请日：2005-08-04
申请人： Kazuhide Hasebe , Atsushi Endo , Mitsuhiro Okada , Jun Ogawa , Akihito Yamamoto , Takashi Nakao , Masaki Kamimura , Yukihiro Ushiku
发明人： Kazuhide Hasebe , Atsushi Endo , Mitsuhiro Okada , Jun Ogawa , Akihito Yamamoto , Takashi Nakao , Masaki Kamimura , Yukihiro Ushiku
IPC分类号： C23C16/44 , H01L21/00 , C23F1/00 , B44C1/22
CPC分类号： H01L21/67248 , C23C16/4405 , H01L21/67109
摘要： A processing system of the present invention includes: a reaction container in which a substrate to be processed is placed, a process-gas supplying mechanism that supplies a process gas into the reaction container at a process to the substrate, a cleaning-gas supplying mechanism that supplies a corrosive cleaning gas into the reaction container at a cleaning process, a gas-discharging-way member connected to the reaction chamber, a heating unit that heats a specific portion of the reaction container and the gas-discharging-way member, a temperature detecting unit that detects a temperature of the specific portion, a temperature controlling unit that controls the heating unit based on a detection value detected by the temperature detecting unit in such a manner that the specific portion becomes to a predetermined target temperature, and a temperature changing unit that changes the target temperature between at the process to the substrate and at the cleaning process. By means of the temperature changing unit, the target temperature is set to a temperature at which adhesion of reaction by-products to the specific portion may be inhibited, at the process to the substrate, while the target temperature is set to a temperature at which corrosion of the specific portion may be inhibited, at the cleaning process.
摘要翻译：本发明的处理系统包括：反应容器，其中放置有待处理的基板，处理气体供给机构，其将处理气体在处理过程中提供给反应容器;清洗气体供给机构在清洁过程中向反应容器提供腐蚀性清洁气体，连接到反应室的气体排出构件，加热反应容器的特定部分的加热单元和气体排出通路构件，温度检测单元，其检测特定部分的温度;温度控制单元，其基于由温度检测单元检测的检测值以特定部分变为预定目标温度的方式控制加热单元;温度控制单元，改变单元，其在过程到基板和清洁过程之间改变目标温度。通过温度变化单元，将目标温度设定为在基板处理时可以抑制反应副产物对特定部分的粘附的温度，同时将目标温度设定为温度在清洗过程中可能会抑制特定部分的腐蚀。

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