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71. 发明授权

US6087254A Technique for elimination of pitting on silicon substrate during gate stack etch 失效
公开(公告)号：US6087254A
公开(公告)日：2000-07-11
申请号：US682935
申请日：1996-07-16
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28052
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

72. 发明授权

US6080645A Method of making a doped silicon diffusion barrier region 失效
标题翻译：制造掺杂硅扩散阻挡区域的方法
公开(公告)号：US6080645A
公开(公告)日：2000-06-27
申请号：US741870
申请日：1996-10-29
申请人： Pai-Hung Pan
发明人： Pai-Hung Pan
IPC分类号： H01L21/28 , H01L29/49 , H01L21/3205
CPC分类号： H01L21/28061 , H01L29/4941
摘要： Methods and apparatus are discussed for forming word line stacks formed of a silicon diffusion barrier region, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.
摘要翻译：讨论了用于形成由掺杂有氧或氮的硅扩散阻挡区形成的字线堆叠的方法和装置，其耦合在底部硅层和导体层之间。通过本发明的方法形成的字线叠层用于0.25μm以下的线宽应用中，具有较低的电阻率和改善的热稳定性。

73. 发明授权

US5925918A Gate stack with improved sidewall integrity 失效
标题翻译：具有改进的侧壁完整性的门叠层
公开(公告)号：US5925918A
公开(公告)日：1999-07-20
申请号：US902808
申请日：1997-07-30
申请人： Zhiqiang Wu , Pai-Hung Pan
发明人： Zhiqiang Wu , Pai-Hung Pan
IPC分类号： H01L21/28 , H01L21/3213 , H01L29/49 , H01L29/78
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/4983 , H01L21/32137 , Y10S257/90 , Y10S257/915
摘要： A process of manufacturing a gate stack is disclosed whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.
摘要翻译：公开了一种制造栅极堆叠的工艺，由此保持了栅极侧壁和基板表面的完整性。氮化物间隔物构造在仅蚀刻到多晶硅层顶部的栅极的侧壁上。这允许在随后的再氧化期间暴露更多的多晶硅侧壁，同时最小化在再氧化期间产生的鸟嘴的影响。在构造氮化物间隔物之后，以两个步骤进行随后的蚀刻，以便使底层活性区域中的衬底表面的降解最小化。

74. 发明授权

US5739066A Semiconductor processing methods of forming a conductive gate and line 失效
标题翻译：形成导电栅极和线路的半导体加工方法
公开(公告)号：US5739066A
公开(公告)日：1998-04-14
申请号：US710353
申请日：1996-09-17
申请人： Pai-Hung Pan
发明人： Pai-Hung Pan
IPC分类号： H01L21/28 , H01L21/3105
CPC分类号： H01L21/28176 , H01L21/28167 , H01L21/28211
摘要： A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of first and second insulating materials and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision and subsequent anisotropic etch of a first insulating material, followed by provision and subsequent anisotropic etch of a second insulating material.
摘要翻译：在衬底上形成导电栅极或栅极线的半导体处理方法包括：a）在衬底上的栅极电介质层上形成导电栅极，所述栅极具有侧壁和与栅极介电层的界面; b）电绝缘栅极侧壁; 以及c）在将所述栅极侧壁电绝缘之后，将所述衬底暴露于有效地氧化与所述栅极介电层的所述栅极界面的至少一部分的氧化条件。根据本发明的一个方面，在提供第一绝缘材料和随后的各向异性蚀刻之后，将衬底暴露于氧化条件下进行步骤，以使栅极侧壁绝缘。根据本发明的另一方面，在提供第一绝缘材料和第二绝缘材料之后进行将衬底暴露于氧化条件的步骤，然后进行其各向异性蚀刻以使栅极侧壁绝缘。根据本发明的另一方面，在提供第一绝缘材料的随后的各向异性蚀刻之后，随后对第二绝缘材料进行随后的各向异性蚀刻，进行将衬底暴露于氧化条件的步骤。

75. 发明授权

US5412246A Low temperature plasma oxidation process 失效
标题翻译：低温等离子体氧化工艺
公开(公告)号：US5412246A
公开(公告)日：1995-05-02
申请号：US186568
申请日：1994-01-26
申请人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
发明人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
IPC分类号： C23C8/36 , H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8242 , H01L27/108 , H01L29/12
CPC分类号： H01L21/32105 , H01L21/02238 , H01L21/02252 , H01L21/31662 , Y10S148/118 , Y10S257/90
摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (
摘要翻译：一种在半导体器件的表面上形成薄膜的工艺。该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1，在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

76. 发明授权

US08492851B2 Structures including an at least partially reoxidized oxide material 失效
标题翻译：包括至少部分再氧化的氧化物材料的结构
公开(公告)号：US08492851B2
公开(公告)日：2013-07-23
申请号：US12120070
申请日：2008-05-13
申请人： Li Li , Pai-Hung Pan
发明人： Li Li , Pai-Hung Pan
IPC分类号： H01L29/78
CPC分类号： H01L21/28008 , H01L21/0223 , H01L21/02238 , H01L21/02255 , H01L21/02351 , H01L21/26506 , H01L21/31662 , H01L21/76213 , H01L21/823412 , H01L21/823807 , H01L29/42368 , H01L29/66575 , Y10S148/116 , Y10S148/118
摘要： Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.
摘要翻译：氧化方法和所得结构包括在衬底上提供氧化物层，然后通过在含有至少一种氧化剂的气氛中垂直离子轰击氧化物层来氧化氧化物层。氧化物层可以设置在衬底中的扩散区域（例如源极和漏极区域）上。氧化物层可以覆盖在衬底上并且靠近衬底上的栅极结构。至少一种氧化剂可以是氧，水，臭氧或过氧化氢，或其混合物。这些氧化方法提供低温氧化工艺，栅极结构中导电层的侧壁的氧化较少，并且较少的电流从栅极结构泄漏到衬底。

77. 发明申请

US20080203542A1 ION-ASSISTED OXIDATION METHODS AND THE RESULTING STRUCTURES 失效
标题翻译：离子辅助氧化方法和结构结构
公开(公告)号：US20080203542A1
公开(公告)日：2008-08-28
申请号：US12120070
申请日：2008-05-13
申请人： Li Li , Pai-Hung Pan
发明人： Li Li , Pai-Hung Pan
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L21/28008 , H01L21/0223 , H01L21/02238 , H01L21/02255 , H01L21/02351 , H01L21/26506 , H01L21/31662 , H01L21/76213 , H01L21/823412 , H01L21/823807 , H01L29/42368 , H01L29/66575 , Y10S148/116 , Y10S148/118
摘要： Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.
摘要翻译：氧化方法和所得结构包括在衬底上提供氧化物层，然后通过在含有至少一种氧化剂的气氛中垂直离子轰击氧化物层来再氧化氧化物层。氧化物层可以设置在衬底中的扩散区域（例如源极和漏极区域）上。氧化物层可以覆盖在衬底上并且靠近衬底上的栅极结构。至少一种氧化剂可以是氧，水，臭氧或过氧化氢，或其混合物。这些氧化方法提供低温氧化工艺，栅极结构中导电层的侧壁的氧化较少，并且较少的电流从栅极结构泄漏到衬底。

78. 发明申请

US20070059943A1 Ion-assisted oxidation methods and the resulting structures 有权
标题翻译：离子辅助氧化方法及其结构
公开(公告)号：US20070059943A1
公开(公告)日：2007-03-15
申请号：US11545017
申请日：2006-10-09
申请人： Li Li , Pai-Hung Pan
发明人： Li Li , Pai-Hung Pan
IPC分类号： H01L21/31 , H01L21/76
CPC分类号： H01L21/28008 , H01L21/0223 , H01L21/02238 , H01L21/02255 , H01L21/02351 , H01L21/26506 , H01L21/31662 , H01L21/76213 , H01L21/823412 , H01L21/823807 , H01L29/42368 , H01L29/66575 , Y10S148/116 , Y10S148/118
摘要： Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.
摘要翻译：氧化方法和所得结构包括在衬底上提供氧化物层，然后通过在含有至少一种氧化剂的气氛中垂直离子轰击氧化物层来再氧化氧化物层。氧化物层可以设置在衬底中的扩散区域（例如源极和漏极区域）上。氧化物层可以覆盖在衬底上并且靠近衬底上的栅极结构。至少一种氧化剂可以是氧，水，臭氧或过氧化氢，或其混合物。这些氧化方法提供低温氧化工艺，栅极结构中导电层的侧壁的氧化较少，并且较少的电流从栅极结构泄漏到衬底。

79. 发明授权

US06744108B1 Doped silicon diffusion barrier region 失效
标题翻译：掺杂硅扩散阻挡区
公开(公告)号：US06744108B1
公开(公告)日：2004-06-01
申请号：US09596936
申请日：2000-06-19
申请人： Pai-Hung Pan
发明人： Pai-Hung Pan
IPC分类号： H01L2976
CPC分类号： H01L21/28061 , H01L29/4941
摘要： Methods and apparatus for forming word line stacks are comprised of a silicon diffusion barrier region, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.
摘要翻译：用于形成字线堆叠的方法和装置由掺杂有氧或氮的硅扩散阻挡区域组成，耦合在底部硅层和导体层之间。通过本发明的方法形成的字线叠层用于0.25μm以下的线宽应用，并具有较低的电阻率和改善的热稳定性。

80. 发明授权

US06599840B2 Material removal method for forming a structure 有权
公开(公告)号：US06599840B2
公开(公告)日：2003-07-29
申请号：US10194833
申请日：2002-07-11
申请人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
发明人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/2815 , H01L21/28525 , H01L21/30608 , H01L21/32134 , H01L21/76232 , H01L21/76237 , H01L21/7624 , H01L21/76838 , H01L21/76897 , H01L27/10817 , H01L28/60 , H01L29/66492 , H01L29/66575
摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

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