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71. 发明申请

US20050145935A1 Memory cell without halo implant 失效
标题翻译：无光晕植入的记忆细胞
公开(公告)号：US20050145935A1
公开(公告)日：2005-07-07
申请号：US10750566
申请日：2003-12-31
申请人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/404 , H01L21/8239 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/76
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/0214 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
摘要翻译：一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷第二种载体。根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结是不偏不倚的一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

72. 发明申请

US20050105342A1 Floating-body dram with two-phase write 失效
标题翻译：浮动车身两相写
公开(公告)号：US20050105342A1
公开(公告)日：2005-05-19
申请号：US10716755
申请日：2003-11-19
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C5/00 , G11C7/00 , G11C11/404 , G11C11/4076 , G11C11/408 , G11C11/4094
CPC分类号： G11C11/4094 , G11C11/404 , G11C11/4076 , G11C11/4085
摘要： A row of floating-body single transistor memory cells is written to in two phases.
摘要翻译：一行浮体单晶体管存储单元分两个阶段写入。

73. 发明授权

US06721222B2 Noise suppression for open bit line DRAM architectures 有权
标题翻译：开放位线DRAM架构的噪声抑制
公开(公告)号：US06721222B2
公开(公告)日：2004-04-13
申请号：US10300398
申请日：2002-11-19
申请人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C702
CPC分类号： G11C11/4097 , G11C7/02 , G11C11/4094
摘要： An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
摘要翻译：开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。在一种方法中，提供虚拟单元和参考单元用于执行信号注入。本发明的原理特别适用于嵌入式DRAM结构，其中各个单元内的低电荷存储容量降低了可实现的信号电压电平。

74. 发明授权

US06567329B2 Multiple word-line accessing and accessor 有权
标题翻译：多个字线访问和访问器
公开(公告)号：US06567329B2
公开(公告)日：2003-05-20
申请号：US09941053
申请日：2001-08-28
申请人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C702
CPC分类号： G11C11/408 , G11C11/4097
摘要： The word-lines and/or bit-lines in a memory are physically arranged to reduce capacitive coupling between signal lines and reference lines. In one embodiment the two bit lines connected to a single sense amplifier are physically separated from each other by bit lines connected to other sense amplifiers. In another embodiment the word-lines are separated from each other by placing them in different metallization layers. In a particular embodiment a single word-line has different portions disposed in different metallization layers.
摘要翻译：物理地布置存储器中的字线和/或位线以减少信号线和参考线之间的电容耦合。在一个实施例中，连接到单个读出放大器的两个位线通过连接到其它读出放大器的位线彼此物理分离。在另一个实施例中，字线通过将它们放置在不同的金属化层中而彼此分离。在特定实施例中，单个字线具有设置在不同金属化层中的不同部分。

75. 发明授权

US06496402B1 Noise suppression for open bit line DRAM architectures 有权
标题翻译：开放位线DRAM架构的噪声抑制
公开(公告)号：US06496402B1
公开(公告)日：2002-12-17
申请号：US09690513
申请日：2000-10-17
申请人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C506
CPC分类号： G11C11/4097 , G11C7/02 , G11C11/4094
摘要： An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
摘要翻译：开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。在一种方法中，提供虚拟单元和参考单元用于执行信号注入。本发明的原理特别适合于在嵌入式DRAM结构中使用，其中各个单元内的低电荷存储容量降低可实现的信号电压电平。

76. 发明授权

US06421269B1 Low-leakage MOS planar capacitors for use within DRAM storage cells 有权
标题翻译：用于DRAM存储单元的低泄漏MOS平面电容器
公开(公告)号：US06421269B1
公开(公告)日：2002-07-16
申请号：US09690687
申请日：2000-10-17
申请人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C1124
CPC分类号： H01L29/66181 , H01L27/0218 , H01L27/10805 , H01L29/94
摘要： A planar capacitor for use within a dynamic random access memory (DRAM) cell is operated within semiconductor depletion during normal storage operations to increase the charge retention time of the capacitor. Operation within semiconductor depletion allows a significant increase in charge retention time in a capacitor for which gate oxide leakage is the predominant leakage mechanism. The voltages that are applied to the storage cell during DRAM operation are controlled so that the storage capacitor within the cell remains in depletion during storage of both a logic zero and a logic one. Although the capacitance of the cell is decreased by operating in depletion, the charge retention time of the cell can be increased by multiple orders of magnitude. In one application, the inventive structures and techniques are implemented within a DRAM device that is embedded within logic circuitry.
摘要翻译：用于动态随机存取存储器（DRAM）单元的平面电容器在正常存储操作期间在半导体耗尽中运行，以增加电容器的电荷保留时间。在半导体耗尽中的操作允许在电容器中的电荷保持时间显着增加，其中栅极氧化物泄漏是主要的泄漏机制。控制在DRAM操作期间施加到存储单元的电压，使得在存储逻辑0和逻辑1期间，单元内的存储电容器保持耗尽。尽管电池的电容通过在耗尽中操作而降低，但电池的电荷保持时间可以增加多个数量级。在一个应用中，本发明的结构和技术在嵌入在逻辑电路内的DRAM器件内实现。

77. 发明授权

US07246215B2 Systolic memory arrays 有权
标题翻译：收缩记忆阵列
公开(公告)号：US07246215B2
公开(公告)日：2007-07-17
申请号：US10721178
申请日：2003-11-26
申请人： Shih-Lien L. Lu , Dinesh Somasekhar , Yibin Ye
发明人： Shih-Lien L. Lu , Dinesh Somasekhar , Yibin Ye
IPC分类号： G06F12/00
CPC分类号： G11C7/1039 , G06F13/1615 , G06F2212/271 , G11C7/10
摘要： A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.
摘要翻译：短暂的延迟和高带宽存储器包括细分为多个存储器阵列的收缩记忆体，包括存储这些存储体的存储体和管线。由于每个存储体的尺寸较小，访问速度更快，因此可以实现更短的延迟和更快的性能。由于流水线而实现了高吞吐量。使用提出的读写机制，在流水线频率处访问存储器。存储器中的每个存储单元都相同并重复，因此减少了设计复杂度。重新配置和组织存储器阵列大小以适应所需的大小和面积参数。

78. 发明授权

US09230636B2 Apparatus for dual purpose charge pump 有权
标题翻译：双用电荷泵装置
公开(公告)号：US09230636B2
公开(公告)日：2016-01-05
申请号：US14137808
申请日：2013-12-20
申请人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
发明人： Pascal A. Meinerzhagen , Jaydeep P. Kulkarni , Muhammad M. Khellah , Cyrille Dray , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
IPC分类号： G11C5/14 , G11C11/4074 , G11C11/16 , G11C16/06 , G11C11/406 , G11C11/4076 , G11C5/06 , G11C11/408
CPC分类号： G11C11/4074 , G11C5/063 , G11C5/14 , G11C5/145 , G11C5/148 , G11C11/1697 , G11C11/406 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/417 , G11C16/06
摘要： Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.
摘要翻译：描述了一种装置，包括：提供第一电源的第一电源节点，第二电源节点和第三电源节点; 第一晶体管，其可操作以耦合所述第一和第二电源节点; 以及电荷泵电路，以一种模式向第三电源节点提供升压电压，并且在另一模式下从第二功率节点恢复电荷。描述了一种存储单元，其包括：可操作以刷新的DRAM; 门极电源节点，其耦合到DRAM以向DRAM提供门控电源; 以及充电回收电路，用于在DRAM被刷新之后从门控电源节点恢复电荷。

79. 发明授权

US07558097B2 Memory having bit line with resistor(s) between memory cells 有权
标题翻译：存储器与存储器单元之间的电阻器具有位线
公开(公告)号：US07558097B2
公开(公告)日：2009-07-07
申请号：US11648399
申请日：2006-12-28
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/413
摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。还公开了其他实施例。

80. 发明申请

US20080158932A1 Memory having bit line with resistor(s) between memory cells 有权
标题翻译：存储器与存储器单元之间的电阻器具有位线
公开(公告)号：US20080158932A1
公开(公告)日：2008-07-03
申请号：US11648399
申请日：2006-12-28
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/413
摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。还公开了其他实施例。

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