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71. 发明申请

US20070267677A1 SINGLE POLY NON-VOLATILE MEMORY DEVICE WITH INVERSION DIFFUSION REGIONS AND METHODS FOR OPERATING THE SAME 有权
标题翻译：具有反向扩散区域的单个聚合非挥发性存储器件及其操作方法
公开(公告)号：US20070267677A1
公开(公告)日：2007-11-22
申请号：US11383924
申请日：2006-05-17
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825
摘要： A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed on top of the dielectric layer. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, an assist gate, or assist gates are formed on the dielectric layer next to and between the control gate and floating gate respectively. The assist gates are used to form inversion diffusion regions in the substrate. By using the assist gates to form inversion diffusion regions, the overall size of the device can be reduced, which can improve device density.
摘要翻译：非易失性存储器件包括其上形成有电介质层的衬底。然后在电介质层的顶部形成控制栅极和浮置栅极。因此，可以使用与常规CMOS工艺兼容的单一多工艺来构造非易失性存储器件。此外，辅助栅极或辅助栅极分别形成在控制栅极和浮置栅极之间和之间的电介质层上。辅助栅极用于在衬底中形成反向扩散区域。通过使用辅助栅极形成反向扩散区域，可以减小器件的整体尺寸，这可以提高器件密度。

72. 发明申请

US20070232000A1 FABRICATING METHOD OF A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的制作方法
公开(公告)号：US20070232000A1
公开(公告)日：2007-10-04
申请号：US11760142
申请日：2007-06-08
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42344 , H01L29/7883 , H01L29/7885
摘要： A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls of the stacked structure and the exposed substrate. A charge storage layer covers over the top and sidewalls of the stacked structure. Also, a pair of auxiliary gates is formed over the substrate beside the charge storage layer, and a gap is between the auxiliary gates and the charge storage layer.
摘要翻译：提供了一种制造非易失性存储器的方法。堆叠结构形成在衬底上，堆叠结构在其上具有栅介电层和浮栅。第一电介质层，第二电介质层和第三电介质层分别形成在层叠结构的顶部和侧壁以及暴露的基板上。电荷存储层覆盖层叠结构的顶部和侧壁。此外，在电荷存储层旁边的基板上形成一对辅助栅极，并且在辅助栅极和电荷存储层之间形成间隙。

73. 发明申请

US20070212800A1 Methods for detecting charge effects during semiconductor processing 审中-公开
标题翻译：在半导体加工过程中检测电荷效应的方法
公开(公告)号：US20070212800A1
公开(公告)日：2007-09-13
申请号：US11370362
申请日：2006-03-08
申请人： Chao-I Wu , Ming Lee , Ming-Chang Kuo
发明人： Chao-I Wu , Ming Lee , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/14
摘要： A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A charge pump current can be used to detect the charging effect during various processing steps.
摘要翻译：半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。可以使用电荷泵电流来检测各种处理步骤中的充电效果。

74. 发明申请

US20070090448A1 Systems and methods for memory structure comprising embedded flash memory 有权
标题翻译：包括嵌入式闪存的存储器结构的系统和方法
公开(公告)号：US20070090448A1
公开(公告)日：2007-04-26
申请号：US11255483
申请日：2005-10-21
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578
摘要： A memory structure that combines multiple embedded flash memory. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. In one aspect, the flash memory cells are stacked on top of the flash memory cells and the flash memory cells share a gate layer. In another aspect, pairs of stacked flash memory cells are stacked on top of each other with each pair isolated by an isolation oxide. In another aspect, pairs of stacked flash memory cells are stacked on top of each other in an un-isolated configuration.
摘要翻译：一种结合多个嵌入式闪存的存储器结构。闪存可用于例如空气替换单元或备用存储器或附加存储器单元。在一个方面，闪速存储器单元堆叠在闪速存储器单元的顶部上，闪存单元共享一个栅极层。在另一方面，堆叠的闪存单元堆叠在彼此的顶部上，每一对由隔离氧化物隔离。在另一方面，堆叠的闪存单元堆叠在彼此之间的非隔离配置中。

75. 发明授权

US5344139A Racket shaft mounting device 失效
标题翻译：球拍轴安装装置
公开(公告)号：US5344139A
公开(公告)日：1994-09-06
申请号：US149300
申请日：1993-11-09
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： A63B49/02
CPC分类号： A63B49/02
摘要： A racket shaft mounting device includes a head frame to hold a network of catgut, and a tubular shaft having a front end connected to the head frame by a connecting device and a rear end terminated to a hand grip, wherein the head frame has two opposite ends fitted one into the other; the connecting device includes a connecting rod having one end fitted into a through hole through the connected two opposite ends of the head frame and an opposite end fitted into the tubular shaft, and a covering layer directly molded on the connecting area between the head frame and the tubular shaft.
摘要翻译：球拍轴安装装置包括：头架，用于保持肠道网;以及管状轴，其前端通过连接装置连接到头架，后端终止于手柄，其中头架具有两个相对的一端装入另一个; 所述连接装置包括连接杆，所述连接杆的一端通过所述头部框架的连接的两个相对端装配到通孔中，并且相对端装配到所述管状轴中，并且覆盖层直接模制在所述头部框架与所述头部框架之间的连接区域上管状轴。

76. 发明授权

US08426906B2 Method and structure for a semiconductor charge storage device 有权
标题翻译：半导体电荷存储装置的方法和结构
公开(公告)号：US08426906B2
公开(公告)日：2013-04-23
申请号：US12106096
申请日：2008-04-18
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： A semiconductor charge storage device includes a semiconductor substrate having a surface region. The semiconductor substrate is characterized by a first conductivity type. A charge trapping material overlies and is in contact with at least a portion of the surface region of the semiconductor substrate. The charge trapping material is characterized by a first dielectric constant and by a first charge trapping capability. The first dielectric constant is higher than a dielectric constant associated with silicon oxide. A dielectric material overlies and is in contact with at least a portion of the charge trapping material. The dielectric material is formed using a conversion of a portion of the charge trapping material for providing a second charge trapping capability. The device also includes a conductive material overlying the second dielectric. The conductive material is capable of receiving an electrical signal to cause electrical charges being trapped in the semiconductor charge storage device.
摘要翻译：半导体电荷存储装置包括具有表面区域的半导体基板。半导体衬底的特征在于第一导电类型。电荷捕获材料覆盖并与半导体衬底的表面区域的至少一部分接触。电荷捕获材料的特征在于第一介电常数和第一电荷俘获能力。第一介电常数高于与氧化硅相关的介电常数。电介质材料覆盖并与电荷捕获材料的至少一部分接触。使用电荷捕获材料的一部分的转换来形成电介质材料，以提供第二电荷俘获能力。该装置还包括覆盖在第二电介质上的导电材料。导电材料能够接收电信号以引起电荷被捕获在半导体电荷存储装置中。

77. 发明授权

US08334182B2 Method for manufacturing non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US08334182B2
公开(公告)日：2012-12-18
申请号：US13117443
申请日：2011-05-27
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for manufacturing a non-volatile memory is provided. The method comprises steps of providing a substrate. Thereafter, a plurality of first doped regions are formed in the substrate and then a plurality of trenches are formed in a portion of the first doped regions. A plurality of second doped regions are formed in a portion of the substrate under the bottoms of the trenches respectively. Then, a charge storage layer is formed conformal to a surface of the substrate and a conductive layer is formed over the substrate, wherein the conductive layer covers the charge storage layer and fills in the trenches.
摘要翻译：提供一种用于制造非易失性存储器的方法。该方法包括提供衬底的步骤。此后，在衬底中形成多个第一掺杂区域，然后在第一掺杂区域的一部分中形成多个沟槽。多个第二掺杂区域分别形成在沟槽底部的衬底的一部分中。然后，形成与基板的表面一致的电荷存储层，并且在基板上形成导电层，其中，导电层覆盖电荷存储层并填充沟槽。

78. 发明申请

US20110267889A1 A HIGH SECOND BIT OPERATION WINDOW METHOD FOR VIRTUAL GROUND ARRAY WITH TWO-BIT MEMORY CELLS 有权
标题翻译：具有双位存储器单元的虚拟接地阵列的高二位操作窗口方法
公开(公告)号：US20110267889A1
公开(公告)日：2011-11-03
申请号：US13184189
申请日：2011-07-15
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/10
CPC分类号： H01L21/28282 , G11C16/0475 , G11C16/0491 , H01L27/11568 , H01L29/7923
摘要： A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.
摘要翻译：公开了一种采用存储器半导体单元的非易失性VG存储器阵列，该存储器半导体单元能够存储与至少一个电绝缘层（例如氧化物）相结合的分层的非导电电荷俘获电介质（例如氮化硅）的两比特信息。。存储器阵列的位线能够传输正电压以到达阵列的存储器单元的源极/漏极区域。公开了一种方法，其包括将阵列的存储单元的空穴注入擦除将存储单元的电压阈值降低到低于单元的初始电压阈值的值。空穴注入诱导的较低电压阈值降低了第二位效应，使得位的编程和未编程电压阈值之间的操作窗口变宽。编程和读取步骤减少阵列中存储单元的泄漏电流。

79. 发明申请

US20110002166A1 TWO-BIT NON-VOLATILE FLASH MEMORY ARRAY 审中-公开
标题翻译：两个非易失性闪存存储阵列
公开(公告)号：US20110002166A1
公开(公告)日：2011-01-06
申请号：US12842046
申请日：2010-07-23
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A memory array comprises a semiconductor substrate, two-bit memory cells, word lines, a gate voltage source, bit lines and bit line control cells. The memory cells have a first and a second source/drain regions, each memory cell includes a dielectric trapping layer, and the dielectric trapping layer is disposed between a first oxide layer and a gate layer. The word lines are coupled to the gate layer. The gate voltage source is coupled to the word lines and configured to apply erase voltages between 14 and 20 volts to the word lines. The bit lines are in electrical communication with the first and the second source/drain regions. The bit line control cells are disposed at the beginning and end of each bit line, the bit line control cells are configured to control the electrical communication of each bit line with the first and the second source/drain regions.
摘要翻译：存储器阵列包括半导体衬底，两位存储器单元，字线，栅极电压源，位线和位线控制单元。存储单元具有第一和第二源极/漏极区域，每个存储器单元包括电介质俘获层，并且电介质俘获层设置在第一氧化物层和栅极层之间。字线耦合到栅极层。栅极电压源被耦合到字线并且被配置为向字线施加14和20伏之间的擦除电压。位线与第一和第二源极/漏极区域电连通。位线控制单元设置在每个位线的开始和结束处，位线控制单元被配置为控制每个位线与第一和第二源/漏区的电通信。

80. 发明申请

US20100311217A1 Non-Volatile Memory Device Having A Nitride-Oxide Dielectric Layer 有权
标题翻译：具有氮化物 - 氧化物介电层的非易失性存储器件
公开(公告)号：US20100311217A1
公开(公告)日：2010-12-09
申请号：US12818057
申请日：2010-06-17
申请人： Chao-I Wu , Tzu-Hsuan Hsu , Hang-Ting Lue , Erh-Kun Lai
发明人： Chao-I Wu , Tzu-Hsuan Hsu , Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L29/513
摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.
摘要翻译：非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

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