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71. 发明授权

US07842548B2 Fixture for P-through silicon via assembly 有权
标题翻译： P-through硅通过组装的夹具
公开(公告)号：US07842548B2
公开(公告)日：2010-11-30
申请号：US12107504
申请日：2008-04-22
申请人： Chien-Hsiun Lee , Chen-Shien Chen , Mirng-Ji Lii , Tjandra Winata Karta
发明人： Chien-Hsiun Lee , Chen-Shien Chen , Mirng-Ji Lii , Tjandra Winata Karta
IPC分类号： H01L21/58
CPC分类号： H01L24/97 , H01L21/486 , H01L21/67184 , H01L21/67207 , H01L21/6835 , H01L23/147 , H01L23/49827 , H01L24/75 , H01L24/81 , H01L25/0655 , H01L2221/68331 , H01L2221/68381 , H01L2224/13316 , H01L2224/16235 , H01L2224/75744 , H01L2224/81005 , H01L2224/81193 , H01L2224/81815 , H01L2224/97 , H01L2924/01005 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/15311 , H01L2924/0105
摘要： A silicon-based wafer such as a TSV interposer wafer having a first and second surfaces wherein a glass carrier is mounted on the second surface by a UV tape is held by a vacuum holder applied on the first surface and the glass carrier is removed from the silicon-based wafer by irradiating the UV tape with a UV light through the glass carrier. The silicon-based wafer is then flipped and placed onto a vacuum plate and secured to the vacuum plate by applying vacuum to the vacuum plate. The vacuum holder is then released from the silicon-based wafer leaving the silicon-based wafer secured to the vacuum plate for subsequent processing steps.
摘要翻译：具有第一表面和第二表面的硅基晶片，其中玻璃载体通过UV带安装在第二表面上，由施加在第一表面上的真空保持器保持，玻璃载体从硅基晶片，通过紫外光照射UV带通过玻璃载体。然后将硅基晶片翻转并放置在真空板上并通过向真空板施加真空而固定到真空板。然后将真空保持器从硅基晶片释放，留下固定到真空板的硅基晶片用于随后的处理步骤。

72. 发明申请

US20100140805A1 Bump Structure for Stacked Dies 有权
标题翻译：堆叠模具的凸起结构
公开(公告)号：US20100140805A1
公开(公告)日：2010-06-10
申请号：US12331900
申请日：2008-12-10
申请人： Hung-Pin Chang , Kuo-Ching Hsu , Chen-Shien Chen , Wen-Chih Chiou , Chen-Hua Yu
发明人： Hung-Pin Chang , Kuo-Ching Hsu , Chen-Shien Chen , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L23/485 , H01L21/74 , H01L21/50
CPC分类号： H01L23/5384 , H01L21/568 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/0231 , H01L2224/02311 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/0557 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/1401 , H01L2224/1701 , H01L2224/81001 , H01L2224/81005 , H01L2224/81193 , H01L2224/812 , H01L2224/81801 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board.
摘要翻译：提供了可用于堆叠管芯配置的凸块结构。通孔形成在半导体衬底中。半导体衬底的背面变薄以暴露通硅通孔。在半导体衬底的背面和通过硅通孔的暴露部分之后形成隔离膜。隔离膜被稀释以重新暴露通硅通孔。在半导体衬底的背面上形成凸起焊盘和再分布线，提供与通孔硅通孔的电连接。沉积和图案化另一个隔离膜，并且形成阻挡层以提供用于连接到外部装置（例如另一个芯片/晶片或电路板）的接触焊盘。

73. 发明申请

US20100090304A1 BONDING PROCESS FOR CMOS IMAGE SENSOR 有权
标题翻译： CMOS图像传感器的结合工艺
公开(公告)号：US20100090304A1
公开(公告)日：2010-04-15
申请号：US12626296
申请日：2009-11-25
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Chen-Cheng Kuo , Chen-Shien Chen , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Chen-Cheng Kuo , Chen-Shien Chen , Shou-Gwo Wuu
IPC分类号： H01L31/0232 , H01L31/18 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/3171 , H01L23/481 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/0557 , H01L2924/01019 , H01L2924/01068 , H01L2924/01078 , H01L2924/04941 , H01L2924/12043 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.
摘要翻译：本公开提供了制造集成电路（IC）的方法。该方法包括在基板的正面上形成电子装置; 在所述基板的前侧形成顶部金属焊盘，所述顶部金属焊盘联接到所述电气装置; 在所述基板的正面上形成钝化层，所述顶部金属焊盘嵌入所述钝化层中; 在钝化层中形成开口，暴露顶部金属垫; 在衬底中形成深沟槽; 在深沟槽和开口中填充导电材料，导致深沟槽中的贯穿晶片通孔（TWV）特征和开口中的焊盘TWV特征，其中顶部金属焊盘通过该沟槽连接到TWV特征 pad-TWV功能; 以及施加抛光工艺以去除过量的导电材料，形成基本平坦的表面。

74. 发明授权

US07666688B2 Method of manufacturing a coil inductor 有权
标题翻译：制造线圈电感器的方法
公开(公告)号：US07666688B2
公开(公告)日：2010-02-23
申请号：US12019688
申请日：2008-01-25
申请人： Kai-Ming Ching , Chen-Shien Chen
发明人： Kai-Ming Ching , Chen-Shien Chen
IPC分类号： H01L21/02
CPC分类号： H01F41/046 , H01F17/0013 , H01F17/0033 , Y10T29/4902
摘要： A method of manufacturing a coil inductor and a coil inductor are provided. A plurality of conductive bottom structures are formed to be lying on a first dielectric layer. A plurality pairs of conductive side structures are then formed, wherein each pair of the conductive side structure stand on top surface of a first end and a second end of each conductive bottom structure respectively; a second dielectric layer is formed on the first dielectric layer, coating the bottom and side structures; and a plurality of conductive top structures are formed to be lying on the second dielectric layer, wherein each conductive top structure electrically connects each pair of the conductive side structures, wherein the conductive bottom structures, the conductive side structures and the conductive top structures together form a conductive coil structure.
摘要翻译：提供一种制造线圈电感器和线圈电感器的方法。多个导电底部结构形成为位于第一介电层上。然后形成多对导电侧结构，其中每对导电侧结构分别位于每个导电底部结构的第一端和第二端的顶表面上; 在第一电介质层上形成第二电介质层，涂覆底部和侧面结构; 并且多个导电顶部结构形成为位于第二介电层上，其中每个导电顶部结构电连接每对导电侧面结构，其中导电底部结构，导电侧面结构和导电顶部结构共同形成导电线圈结构。

75. 发明申请

US20080174002A1 Stress relieving layer for flip chip packaging 有权
标题翻译：用于倒装芯片封装的应力消除层
公开(公告)号：US20080174002A1
公开(公告)日：2008-07-24
申请号：US11655844
申请日：2007-01-22
申请人： Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
发明人： Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
IPC分类号： H01L23/488 , H01L21/00
CPC分类号： H01L23/49816 , H01L21/4853 , H01L23/49827 , H01L24/02 , H01L24/11 , H01L24/16 , H01L2224/02319 , H01L2224/02321 , H01L2224/0401 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.
摘要翻译：提供一种制造半导体封装的方法。在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并与暴露的通孔塞的表面接触。然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。在多个通孔塞的相对端的表面上形成多个UBM层。多个焊料凸起形成并安装在UBM层上。提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。多个焊球形成并安装在第二基板的第二表面上。第三衬底安装到焊球。

76. 发明申请

US20080122114A1 BONDING STRUCTURES AND METHODS OF FORMING BONDING STRUCTURES 有权
标题翻译：粘结结构和形成粘结结构的方法
公开(公告)号：US20080122114A1
公开(公告)日：2008-05-29
申请号：US11563490
申请日：2006-11-27
申请人： Szu Wei Lu , Mirng-Ji Lii , Chen-Shien Chen , Hua-Shu Wu , Jerry Tzou
发明人： Szu Wei Lu , Mirng-Ji Lii , Chen-Shien Chen , Hua-Shu Wu , Jerry Tzou
IPC分类号： H01L21/50 , H01L23/52
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3171 , H01L23/495 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/50 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/32145 , H01L2224/45144 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48229 , H01L2224/48247 , H01L2224/48624 , H01L2224/48647 , H01L2225/0651 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/10253 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/00014 , H01L2924/04953 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.
摘要翻译：半导体结构包括第一基板和粘合在第一基板上的第二基板。第一衬底包括形成在第一衬底上的钝化层。钝化层包括至少一个第一开口，暴露在第一衬底上形成的第一焊盘。第二基板包括与第一开口对准并面向第一开口的至少一个第二开口。

77. 发明申请

US20070021038A1 CMP APPARATUS AND PROCESS SEQUENCE METHOD 有权
标题翻译： CMP装置和方法序列方法
公开(公告)号：US20070021038A1
公开(公告)日：2007-01-25
申请号：US11470407
申请日：2006-09-06
申请人： Chen-Shien Chen , Yai-Yei Huang , Ming-Hsiang Kao , Yih-Shung Lin , Winata Tjandra
发明人： Chen-Shien Chen , Yai-Yei Huang , Ming-Hsiang Kao , Yih-Shung Lin , Winata Tjandra
IPC分类号： B24B49/00
CPC分类号： B24B21/04 , B24B37/345 , B24B49/02
摘要： A CMP apparatus and process sequence. The CMP apparatus includes multiple polishing pads or belts and an in-line metrology tool which is interposed between adjacent polishing pads or belts in the apparatus. A material layer on each of multiple wafers is successively polished on the polishing pads or belts. The metrology tool is used to measure the thickness of a material layer being polished on each of successive wafers in a lot prior to the final polishing step, in order to precisely polish the layer to a desired target thickness at the final polishing step. This renders unnecessary an additional process cycle to polish the layer on each wafer to the desired target thickness. The metrology tool may be modularized as a unit with the polishing pads or belts.
摘要翻译： CMP装置和处理顺序。 CMP装置包括多个抛光垫或带以及插入在装置中的相邻抛光垫或带之间的在线计量工具。在多个晶片的每一个上的材料层在抛光垫或带上连续抛光。测量工具用于测量在最终抛光步骤之前在批次中的每个连续晶片上抛光的材料层的厚度，以便在最终抛光步骤中将层精确抛光到所需目标厚度。这使得不需要额外的处理循环来将每个晶片上的层抛光到期望的目标厚度。测量工具可以模块化为具有抛光垫或带的单元。

78. 发明授权

US08912649B2 Dummy flip chip bumps for reducing stress 有权
标题翻译：用于减轻压力的虚拟倒装芯片凸块
公开(公告)号：US08912649B2
公开(公告)日：2014-12-16
申请号：US13211438
申请日：2011-08-17
申请人： Sheng-Yu Wu , Tin-Hao Kuo , Chita Chuang , Chen-Shien Chen
发明人： Sheng-Yu Wu , Tin-Hao Kuo , Chita Chuang , Chen-Shien Chen
IPC分类号： H01L23/498 , H01L21/50 , H01L21/60 , H01L23/00 , H01L23/31 , H01L23/532 , H01L23/58 , H01L23/522 , H01L21/56
CPC分类号： H01L24/17 , H01L21/563 , H01L23/3171 , H01L23/522 , H01L23/53238 , H01L23/562 , H01L23/585 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2021/60255 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05541 , H01L2224/05569 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05671 , H01L2224/05684 , H01L2224/06102 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/14152 , H01L2224/14179 , H01L2224/16237 , H01L2224/16238 , H01L2224/17104 , H01L2224/17517 , H01L2224/73204 , H01L2224/81007 , H01L2224/81101 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2924/01029 , H01L2924/01047 , H01L2924/04941 , H01L2924/04953 , H01L2924/15787 , H01L2924/15788 , H01L2924/35 , H01L2924/3511 , H01L2924/00014 , H01L2924/014 , H01L2924/206 , H01L2924/00
摘要： A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
摘要翻译：一种器件包括在衬底上的金属焊盘。钝化层包括在金属焊盘上的部分。后钝化互连（PPI）电耦合到金属焊盘，其中PPI包括在金属焊盘和钝化层上的部分。聚合物层在PPI之上。虚设凸块在聚合物层之上，其中虚设凸块与聚合物层下方的导电特征电绝缘。

79. 发明授权

US08901736B2 Strength of micro-bump joints 有权
标题翻译：微凸点接头的强度
公开(公告)号：US08901736B2
公开(公告)日：2014-12-02
申请号：US12789696
申请日：2010-05-28
申请人： Wen-Wei Shen , Chen-Shien Chen , Chen-Cheng Kuo , Ming-Fa Chen , Rung-De Wang
发明人： Wen-Wei Shen , Chen-Shien Chen , Chen-Cheng Kuo , Ming-Fa Chen , Rung-De Wang
IPC分类号： H01L23/48 , H01L23/31 , H01L25/065
CPC分类号： H01L24/16 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/03614 , H01L2224/0401 , H01L2224/05017 , H01L2224/05023 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/1146 , H01L2224/11823 , H01L2224/11831 , H01L2224/1191 , H01L2224/13005 , H01L2224/13018 , H01L2224/13019 , H01L2224/13076 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/1369 , H01L2224/16145 , H01L2224/16148 , H01L2224/16238 , H01L2224/81193 , H01L2224/81345 , H01L2224/81801 , H01L2224/81815 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/35 , Y10T428/12361 , Y10T428/12396 , H01L2924/00 , H01L2924/00012 , H01L2924/01047 , H01L2924/206 , H01L2224/05552
摘要： A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.
摘要翻译：一种装置包括：包括金属凸块的工件; 以及具有直接在金属凸块上的部分的介电层。金属凸块和电介质层部分的表面形成界面。在金属凸块上方形成金属涂层并与金属凸块接触。金属表面从介电层上延伸到界面的下方。

80. 发明申请

US20140070403A1 Packaging Methods and Packaged Devices 有权
标题翻译：包装方法和包装设备
公开(公告)号：US20140070403A1
公开(公告)日：2014-03-13
申请号：US13612588
申请日：2012-09-12
申请人： Kuo Lung Pan , Ming Hung Tseng , Chen-Shien Chen
发明人： Kuo Lung Pan , Ming Hung Tseng , Chen-Shien Chen
IPC分类号： H01L21/56 , H01L23/498
CPC分类号： H01L23/3121 , H01L21/4846 , H01L21/56 , H01L21/6835 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/50 , H01L2224/12105 , H01L2224/131 , H01L2224/19 , H01L2224/2919 , H01L2224/32225 , H01L2224/73253 , H01L2224/73267 , H01L2224/83005 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die.
摘要翻译：公开了包装方法和包装装置。在一个实施例中，一种封装半导体器件的方法包括在载体上形成第一再分布层（RDL），以及在第一RDL上形成多个通过组装通孔（TAV）。集成电路管芯耦合在第一RDL上，并且模制化合物形成在第一RDL，TAV和集成电路管芯上。在模制化合物，TAV和集成电路模具上形成第二RDL。

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