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    • 73. 发明授权
    • Driving circuit of a ferroelectric memory device and a method for
driving the same
    • 铁电存储器件的驱动电路及其驱动方法
    • US5414654A
    • 1995-05-09
    • US133253
    • 1993-10-08
    • Yasushi KubotaShigeo Onishi
    • Yasushi KubotaShigeo Onishi
    • G11C11/22G11C14/00H01L21/822H01L21/8242H01L21/8246H01L27/04H01L27/10H01L27/105H01L27/108
    • G11C11/22
    • A ferroelectric memory device according to the present invention comprises a plurality of bit lines carrying data signals and voltage signals, every adjacent two of the bit lines being paired to form a plurality of bit line pairs; sense amplifiers connected to each of the bit line pairs; a plurality of memory cells for storing data, each memory cell having a first capacitor and a first switching element, the first capacitor being connected to one of the bit lines via the first switching element, wherein the first capacitor includes a capacitor insulating film, at least one portion of the capacitor insulating film being formed of a ferroelectric material; a plurality of dummy cells for storing a reference voltage, each dummy cell having a second capacitor and a second switching element, the second capacitor being connected to one of the bit lines via the second switching element, wherein the second capacitor includes the capacitor insulating film at least one portion of the capacitor insulating film being formed of a ferroelectric material; a first common electrode line for controlling a voltage to be applied to the first capacitor; a second common electrode line for controlling a voltage to be applied to the second capacitor; a first word line for controlling the first switching element; and a second word line for controlling the second switching element, wherein a plurality of the memory cells and at least one of the dummy cells are connected to each bit line.
    • 根据本发明的铁电存储器件包括承载数据信号和电压信号的多个位线,每个相邻的两个位线被配对以形成多个位线对; 连接到每个位线对的读出放大器; 用于存储数据的多个存储单元,每个存储单元具有第一电容器和第一开关元件,所述第一电容器经由所述第一开关元件连接到所述位线之一,其中所述第一电容器包括电容器绝缘膜, 所述电容绝缘膜的至少一部分由铁电体形成; 用于存储参考电压的多个虚拟单元,每个虚设单元具有第二电容器和第二开关元件,所述第二电容器经由所述第二开关元件连接到所述位线之一,其中所述第二电容器包括所述电容器绝缘膜 电容器绝缘膜的至少一部分由铁电材料形成; 用于控制施加到第一电容器的电压的第一公共电极线; 用于控制施加到第二电容器的电压的第二公共电极线; 用于控制第一开关元件的第一字线; 以及用于控制第二开关元件的第二字线,其中多个存储单元和至少一个虚设单元连接到每个位线。
    • 74. 发明授权
    • Semiconductor memory device of alternately-activated open bit-line
architecture
    • 半导体存储器件交替激活开放位线架构
    • US5383159A
    • 1995-01-17
    • US120823
    • 1993-09-15
    • Yasushi Kubota
    • Yasushi Kubota
    • G11C11/401G11C7/18G11C11/4097H01L21/8242H01L27/108G11C7/00
    • G11C11/4097G11C7/18
    • A semiconductor memory device of alternately-activated open bit-line architecture is provided wherein paired bit lines extend from opposite sides of sense amplifiers that are arranged in one direction and every other bit line is activated through activation of a word line intersecting the bit lines. The sense amplifiers in the neighboring first and second rows alternate with each other in a staggering manner. The bit lines extending from the sense amplifiers of the first row in a first direction and the bit lines extending from the sense amplifiers in the opposite, second direction constitute a bit line group between the first and second rows. Word lines and dummy word lines intersect the bit line group. In operation, signals opposite in phase to each other are applied to a selected word line and a corresponding dummy word line from a control section so that memory cells connected to the selected word line are electrically connected with the bit lines while the dummy cells connected with the same bit lines are electrically disconnected from these bit lines.
    • 提供交替激活的开放位线架构的半导体存储器件,其中成对的位线从沿一个方向布置的读出放大器的相对侧延伸,并且通过激活与位线相交的字线来激活每隔一个位线。 相邻的第一和第二行中的读出放大器以交错的方式彼此交替。 从第一行的读出放大器沿第一方向延伸的位线和从相反的第二方向的读出放大器延伸的位线构成第一和第二行之间的位线组。 字线和虚拟字线与位线组相交。 在操作中,相互相反的信号被施加到来自控制部分的选定字线和对应的虚拟字线,使得连接到所选字线的存储器单元与位线电连接,而虚拟单元与 相同的位线与这些位线电断开。
    • 77. 发明申请
    • OPTICALLY ACTIVE DIBENZAZEPINE DERIVATIVES
    • 光学活性二苯并恶唑衍生物
    • US20110034688A1
    • 2011-02-10
    • US12936415
    • 2009-04-08
    • Yasushi KubotaTsutomu Inoue
    • Yasushi KubotaTsutomu Inoue
    • C07D493/04
    • C07D317/60C07D491/06C07D491/16C07D491/20
    • It is to provide a novel optically active dibenzazepine derivative having a high utility value as an asymmetric phase-transfer catalyst. It is an optically active 6,7-dihydro-5H-dibenzo[c,e]azepine derivative represented by the following formula (1′), (wherein R represents a divalent organic group for cross-linking the 1st position and the 11th position; R1 and R2 are the same or different, and represent a hydrogen atom, halogen atom, or organic group, or R1 and R2 together represent a divalent organic group; R3′and R4′ are the same or different and represent a monovalent organic group, or R3′ and R4′ together form an organic group that forms a cyclic structure comprising an onium nitrogen atom; Ar represents a monovalent organic group; * represents optical activity, i.e., that one axially asymmetric isomer is present in excess of the other axially asymmetric isomer with respect to a bond axis that constitutes the biphenyl structure of the compound; and X− represents a counter anion).
    • 提供作为不对称相转移催化剂的具有高效用价值的新颖的光学活性二苯并氮杂衍生物。 它是由下式(1')表示的光学活性的6,7-二氢-5H-二苯并[c,e]吖庚因衍生物,其中R表示用于交联第1位和第11位的二价有机基 R 1和R 2相同或不同,表示氢原子,卤素原子或有机基团,或者R 1和R 2一起表示二价有机基团; R 3'和R 4'相同或不同,表示一价有机基团 或R3'和R4'一起形成形成包含鎓氮原子的环状结构的有机基团; Ar表示一价有机基团; *表示光学活性,即一种轴向不对称异构体存在于另一种轴向 相对于构成化合物的联苯结构的键轴的不对称异构体; X-表示抗衡阴离子)。
    • 79. 发明授权
    • Integrated circuit for scan driving
    • 用于扫描驱动的集成电路
    • US07714827B2
    • 2010-05-11
    • US10717235
    • 2003-11-18
    • Yasushi KubotaSeiji Murakami
    • Yasushi KubotaSeiji Murakami
    • G09G3/36
    • G09G3/3266G09G3/20G09G3/3208G09G2310/0267G09G2310/0283G09G2310/08
    • An integrated circuit is provided for scan driving that can significantly reduce the chip size. In first region AODD, odd-numbered output pads OUT1, OUT3, . . . OUT173, OUT175, driver circuits DR1, DR3, . . . DR173, DR175, and flip-flops SREG1, SREG3, . . . SREG173, SREG175 in an order corresponding to the order of the odd-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction). In second region AEVEN, even-numbered output pads OUT2, OUT4, . . . OUT174, OUT176, driver circuits DR2, DR4, . . . DR174, DR176, and flip-flops SREG2, SREG4, . . . SREG174, SREG176 in an order corresponding to the order of the even-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction).
    • 提供了可以显着降低芯片尺寸的扫描驱动的集成电路。 在第一区域AODD中,奇数编号的输出焊盘OUT1,OUT3,...。 。 。 OUT173,OUT175,驱动电路DR1,DR3,。 。 。 DR173,DR175和触发器SREG1,SREG3,。 。 。 SREG173,SREG175以与奇数扫描线的顺序对应的顺序分别排列成X方向的列,并且同时,输出焊盘OUTi,驱动电路DRi和触发器SREGi对应于 扫描线在Y方向(芯片宽度方向)排列成同一行。 在第二区域AEVEN中,偶数输出焊盘OUT2,OUT4。 。 。 OUT174,OUT176,驱动电路DR2,DR4,。 。 。 DR174,DR176和触发器SREG2,SREG4, 。 。 SREG174,SREG176以与偶数扫描线的顺序相对应的顺序分别排列成X方向的列,并且同时,输出焊盘OUTi,驱动电路DRi和触发器SREGi对应于 扫描线在Y方向(芯片宽度方向)排列成同一行。