专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20100061146A1 Nonvolatile Memory Devices Including Variable Resistive Elements 有权
标题翻译：包括可变电阻元件的非易失性存储器件
公开(公告)号：US20100061146A1
公开(公告)日：2010-03-11
申请号：US12556787
申请日：2009-09-10
申请人： Byung-Gil Choi , Hye-Jin Kim
发明人： Byung-Gil Choi , Hye-Jin Kim
IPC分类号： G11C11/00 , G11C7/04 , G11C5/14
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/72
摘要： A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.
摘要翻译：非易失性存储器件可以包括存储单元阵列，该存储单元阵列具有以矩阵形式布置的多个非易失性存储单元，包括多行非易失性存储单元。多个字线中的每一个可以与矩阵的相应行的非易失性存储器单元耦合。行解码器可以耦合到多个字线，其中行解码器被配置为使用具有响应于温度变化来调整的电平的行偏置来禁用至少一个字线。这种非易失性存储器件可以以减少的待机电流工作。

72. 发明申请

US20100027327A1 Nonvolatile Memory Devices Having Variable-Resistance Memory Cells and Methods of Programming the Same 有权
标题翻译：具有可变电阻存储单元的非易失性存储器件及其编程方法
公开(公告)号：US20100027327A1
公开(公告)日：2010-02-04
申请号：US12498549
申请日：2009-07-07
申请人： Won-Ryul Chung , Byung-Gil Choi , In-Cheol Shin , Ki-Won Lim
发明人： Won-Ryul Chung , Byung-Gil Choi , In-Cheol Shin , Ki-Won Lim
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C13/0038 , G11C8/10 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/72 , G11C2213/79
摘要： Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.
摘要翻译：非易失性存储器件包括可变电阻存储器单元阵列和电耦合到阵列的写入驱动器。写入驱动器被配置为在用于编程所述阵列中的可变电阻存储器单元的操作期间，在具有至少两个不相等的位线电压的阶梯序列的驱动可变电阻存储器单元阵列中的位线。至少两个不等位线电压的阶梯级序列包括第一步骤的预充电电压（例如Vcc-Vth）和跟随第一步骤的第二步骤的较高升压电压（例如，Vpp-Vth）。

73. 发明申请

US20090296459A1 Nonvolatile Memory Device Using Variable Resistive Element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20090296459A1
公开(公告)日：2009-12-03
申请号：US12476875
申请日：2009-06-02
申请人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
发明人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00 , G11C8/10 , G11C7/06
CPC分类号： G11C13/0023 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.
摘要翻译：非易失性存储器件可以包括具有排列成行和列阵列的多个非易失性存储单元的存储单元阵列。多个位线中的每一个可以耦合到阵列的各个列中的非易失性存储器单元，并且多个列选择开关中的每一个可以耦合到相应的一个位线。列解码器可以耦合到多个列选择开关，并且列解码器可以被配置为使用具有施加到列选择中的第一个的第一信号电平的第一列选择信号来选择位线中的第一位开关。列解码器还可以被配置为使用具有第二信号电平的第二列选择信号来选择位线中的第二位，其中第二信号电平施加到第二信号电平不同于第一信号电平的列选择开关中的第二信号电平。

74. 发明申请

US20060274574A1 Phase-change memory device and method of writing a phase-change memory device 有权
公开(公告)号：US20060274574A1
公开(公告)日：2006-12-07
申请号：US11502563
申请日：2006-08-11
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C2013/0078 , G11C2013/0092
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

75. 发明授权

US08243508B2 Resistive memory devices using assymetrical bitline charging and discharging 有权
标题翻译：使用不对称位线充电和放电的电阻式存储器件
公开(公告)号：US08243508B2
公开(公告)日：2012-08-14
申请号：US13216832
申请日：2011-08-24
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00 , G11C8/08
CPC分类号： G11C7/18 , G11C7/12 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/004 , G11C13/0069
摘要： A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.
摘要翻译：非易失性存储器件包括多个存储体，每个存储体包括多个非易失性电阻存储单元（例如PRAM单元）。该设备还包括由存储体共享的写入全局位线和由存储体共享的读出的全局位线。该装置还包括控制电路，其被配置为使用读写全局位线在第一存储体中使用读出的全局位线从第一存储体中的选定的非易失性存储单元读取数据，从而将数据写入到第一存储体中的选定的非易失性存储单元，写入全局位线的时间段比流经第一存储体的非易失性存储单元的写入电流的淬灭时间长。

76. 发明授权

US08228720B2 Nonvolatile memory devices including variable resistive elements 有权
标题翻译：包括可变电阻元件的非易失性存储器件
公开(公告)号：US08228720B2
公开(公告)日：2012-07-24
申请号：US12556787
申请日：2009-09-10
申请人： Byung-Gil Choi , Hye-Jin Kim
发明人： Byung-Gil Choi , Hye-Jin Kim
IPC分类号： G11C7/04 , G11C8/08 , G11C11/21 , G11C8/10
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/72
摘要： A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.
摘要翻译：非易失性存储器件可以包括存储单元阵列，该存储单元阵列具有以矩阵形式布置的多个非易失性存储单元，包括多行非易失性存储单元。多个字线中的每一个可以与矩阵的相应行的非易失性存储器单元耦合。行解码器可以耦合到多个字线，其中行解码器被配置为使用具有响应于温度变化调节的电平的行偏置来禁用至少一个字线。这种非易失性存储器件可以以减少的待机电流工作。

77. 发明授权

US08199603B2 Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same 有权
标题翻译：具有可变电阻存储单元的非易失性存储器件及其编程方法
公开(公告)号：US08199603B2
公开(公告)日：2012-06-12
申请号：US12498549
申请日：2009-07-07
申请人： Won-Ryul Chung , Byung-Gil Choi , In-Cheol Shin , Ki-Won Lim
发明人： Won-Ryul Chung , Byung-Gil Choi , In-Cheol Shin , Ki-Won Lim
IPC分类号： G11C8/00
CPC分类号： G11C13/0038 , G11C8/10 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/72 , G11C2213/79
摘要： Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.
摘要翻译：非易失性存储器件包括可变电阻存储器单元阵列和电耦合到阵列的写入驱动器。写入驱动器被配置为在用于编程所述阵列中的可变电阻存储器单元的操作期间，在具有至少两个不相等的位线电压的阶梯序列的驱动可变电阻存储器单元阵列中的位线。至少两个不等位线电压的阶梯级序列包括第一步骤的预充电电压（例如Vcc-Vth）和跟随第一步骤的第二步骤的较高升压电压（例如，Vpp-Vth）。

78. 发明申请

US20110317484A1 RESISTIVE MEMORY DEVICES USING ASSYMETRICAL BITLINE CHARGING AND DISCHARGING 有权
标题翻译：使用组合式电子充电和放电的电阻式存储器件
公开(公告)号：US20110317484A1
公开(公告)日：2011-12-29
申请号：US13216832
申请日：2011-08-24
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C7/12 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/004 , G11C13/0069
摘要： A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.
摘要翻译：非易失性存储器件包括多个存储体，每个存储体包括多个非易失性电阻存储单元（例如PRAM单元）。该设备还包括由存储体共享的写入全局位线和由存储体共享的读出的全局位线。该装置还包括控制电路，其被配置为使用读写全局位线在第一存储体中使用读出的全局位线从第一存储体中的选定的非易失性存储单元读取数据，从而将数据写入到第一存储体中的选定的非易失性存储单元，写入全局位线的时间段比流经第一存储体的非易失性存储单元的写入电流的淬灭时间长。

79. 发明授权

US08081501B2 Multi-level nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的多级非易失性存储器件
公开(公告)号：US08081501B2
公开(公告)日：2011-12-20
申请号：US12398364
申请日：2009-03-05
申请人： Byung-Gil Choi , Du-Eung Kim
发明人： Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2213/72
摘要： A multi-level nonvolatile memory device using variable resistive element with improved reliability of read operations is provided. A multi-level nonvolatile memory device comprises a multi-level memory which includes a resistance element, wherein the resistance level of the resistance element is variable depending on data stored in the multi-level memory cell, and a read circuit which provides the multi level memory cell with a read bias and performs a sensing operation in response to the read bias, wherein the read bias has at least two levels during a read cycle.
摘要翻译：提供了使用可变电阻元件的多级非易失性存储器件，其具有改进的读取操作的可靠性。一种多级非易失性存储器件，包括一个包括电阻元件的多电平存储器，其中电阻元件的电阻电平根据存储在多电平存储单元中的数据而变化，以及提供多电平的读取电路具有读取偏置的存储单元并且响应于读取偏置执行感测操作，其中读取偏压在读取周期期间具有至少两个电平。

80. 发明授权

US08077496B2 Nonvolatile memory device and method of driving the same 失效
标题翻译：非易失存储器件及其驱动方法
公开(公告)号：US08077496B2
公开(公告)日：2011-12-13
申请号：US12585730
申请日：2009-09-23
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C2013/009
摘要： A nonvolatile memory and a method of driving the same are provided, which adopt an improved write verify operation. The method of driving a nonvolatile memory device having variable resistance memory cells, bit lines coupled to the variable resistance memory cells, and column selection transistors coupled between the variable resistance memory cells and the bit lines to receive a first control voltage being applied to their gates, includes making the first control voltage at a first level, and changing a resistance of the variable resistance memory cells by providing a write bias to the variable resistance cells; verifying and reading whether the changed resistance enters into a specified resistance window; and changing the first control voltage to a second level that is different from the first level, and changing the resistance of the variable resistance memory cells by providing the write bias to the variable resistance memory cells.
摘要翻译：提供了一种非易失性存储器及其驱动方法，其采用改进的写校验操作。驱动具有可变电阻存储单元的非易失性存储器件的方法，耦合到可变电阻存储单元的位线和耦合在可变电阻存储单元与位线之间的列选择晶体管，以接收施加到其栅极的第一控制电压包括使第一控制电压处于第一电平，并通过向可变电阻单元提供写入偏置来改变可变电阻存储单元的电阻; 验证和读取改变的电阻是否进入指定的电阻窗口; 以及将所述第一控制电压改变到与所述第一电平不同的第二电平，以及通过向所述可变电阻存储单元提供所述写入偏置来改变所述可变电阻存储单元的电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式