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71. 发明申请

US20090235059A1 QUALIFICATION OF CONDITIONAL DEBUG INSTRUCTIONS BASED ON ADDRESS 有权
标题翻译：基于地址的条件调试指令的资格
公开(公告)号：US20090235059A1
公开(公告)日：2009-09-17
申请号：US12049984
申请日：2008-03-17
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F9/30189
摘要： A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.
摘要翻译：处理器实现支持基于其可寻址存储器中的相应地址来选择用于调试指令实例的执行模式可以提供用于以允许指令的某些实例以调试语义来操作的方式来执行调试指令的有吸引力的机制，同时通过执行它们与无操作（NOP）语义。在一些实施例中，可操作执行语义的选择可以基于特定调试指令实例驻留在其中的存储器页的属性。在一些实施例中，可以对地址空间的部分进行限定（例如，使用存储在边界寄存器中的值和特定调试指令实例的地址与定界部分进行比较以选择适当的执行语义在一些实施例中，可以使用两种类型的评估在为特定调试指令实例选择适当的执行语义。

72. 发明申请

US20090213668A1 ADJUSTABLE PIPELINE IN A MEMORY CIRCUIT 有权
标题翻译：可调节管线在存储器电路中
公开(公告)号：US20090213668A1
公开(公告)日：2009-08-27
申请号：US12034888
申请日：2008-02-21
申请人： Shayan Zhang , William C. Moyer , Huy B. Nguyen
发明人： Shayan Zhang , William C. Moyer , Huy B. Nguyen
IPC分类号： G11C7/00
CPC分类号： G06F12/0855 , Y02D10/13
摘要： A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon.
摘要翻译：用于操作改善存储器电路的性能的存储器电路和/或用于存储器电路的至少一些操作点的功率消耗的技术包括至少部分地基于存储器的工作点来调节多个操作流水线级。在本发明的至少一个实施例中，用于操作存储器电路的方法包括至少部分地基于由存储器电路产生的反馈信号来选择操作存储器电路的模式。该技术包括基于所选存储器电路的操作模式，使用多个流水线级操作存储器电路。在本发明的至少一个实施例中，该技术包括感测与各个流水线级相关联的定时裕度，并且基于此产生反馈信号。

73. 发明授权

US07574564B2 Replacement pointer control for set associative cache and method 有权
标题翻译：用于设置关联缓存和方法的替换指针控件
公开(公告)号：US07574564B2
公开(公告)日：2009-08-11
申请号：US11382903
申请日：2006-05-11
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0864 , G06F12/126
摘要： A set associative cache includes a plurality of sets, where each set has a plurality of ways. The set associative cache has a plurality of replacement pointers where each set of the plurality of sets has a corresponding replacement pointer within the plurality of replacement pointers, and the corresponding replacement pointer indicates a way of the set. A cache command is provided which specifies a set of the plurality of sets and which specifies a replacement way value. In response to the cache command, a current way value of the replacement pointer corresponding to the specified set is replaced with the replacement way value. The cache may further include way locking control circuitry which indicates whether or not one or more ways is locked. By indicating a locked way with the replacement way value, a locked way can be overridden and thus be used for a subsequent cache line fill.
摘要翻译：集合关联高速缓存包括多个集合，其中每个集合具有多个方式。集合关联高速缓存具有多个替换指针，其中多个集合中的每个集合在多个替换指针之间具有对应的替换指针，并且相应的替换指针指示该集合的一种方式。提供了缓存命令，其指定多个集合的集合并且指定替换方式值。响应于缓存命令，与替换方式值替换与指定集合对应的替换指针的当前方式值。高速缓存还可以包括方向锁定控制电路，其指示一个或多个方式是否被锁定。通过用替代方式值指示锁定方式，锁定方式可以被覆盖，从而被用于后续的高速缓存行填充。

74. 发明授权

US07539906B2 System for integrated data integrity verification and method thereof 有权
标题翻译：用于集成数据完整性验证的系统及其方法
公开(公告)号：US07539906B2
公开(公告)日：2009-05-26
申请号：US11094593
申请日：2005-03-30
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are accessed to obtain a first accumulated value and the first accumulated value is compared with a first expected accumulated value. In accordance with a second technique, a first plurality of load operations are performed at a processor to access data values stored in a first sequence of fields of a memory. The data values are accumulated in one or more accumulators of the processor to generate a first accumulated value and it is determined whether the memory has been corrupted based on a comparison of the first accumulated value to a first expected accumulation value.
摘要翻译：根据一种技术，在处理器处接收与处理器和存储器之间的数据传输相关联的第一多个值，并且第一多个值的至少一个子集被累积在一个或多个累加器中。访问一个或多个累加器以获得第一累积值，并将第一累加值与第一预期累加值进行比较。根据第二技术，在处理器处执行第一多个加载操作以访问存储在存储器的第一字段序列中的数据值。数据值被积累在处理器的一个或多个累加器中以产生第一累积值，并且基于第一累积值与第一预期累加值的比较来确定存储器是否已被破坏。

75. 发明申请

US20090100254A1 DEBUG INSTRUCTION FOR USE IN A DATA PROCESSING SYSTEM 有权
标题翻译：用于数据处理系统的调试指令
公开(公告)号：US20090100254A1
公开(公告)日：2009-04-16
申请号：US11871847
申请日：2007-10-12
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/44
CPC分类号： G06F11/3656 , G06F9/3005 , G06F9/30072 , G06F9/30181
摘要： A method includes providing a debug instruction and providing a debug control register field, where if the debug control register field has a first value, the debug instruction executes a debug operation and where if the debug control register field has a second value, the debug instruction is to be executed as a no-operation (NOP) instruction. A data processing system includes instruction fetch circuitry for receiving a debug instruction, a debug control register field, and debug execution control circuitry for controlling execution of the debug instruction in a first manner if the debug control register field has a first value and in a second manner if the debug control register field has a second value, where in the first manner a debug operation is performed and in the second manner no debug operation is performed.
摘要翻译：一种方法包括提供调试指令并提供调试控制寄存器字段，其中如果调试控制寄存器字段具有第一值，则调试指令执行调试操作，并且如果调试控制寄存器字段具有第二值，则调试指令将作为无操作（NOP）指令执行。数据处理系统包括用于接收调试指令的指令提取电路，调试控制寄存器字段和调试执行控制电路，用于如果调试控制寄存器字段具有第一值，则以第一方式控制调试指令的执行如果调试控制寄存器字段具有第二值，则以第一种方式执行调试操作，并且在第二方式中不执行调试操作。

76. 发明申请

US20090077291A1 COMMUNICATION STEERING FOR USE IN A MULTI-MASTER SHARED RESOURCE SYSTEM 有权
标题翻译：用于多主共享资源系统的通信方向
公开(公告)号：US20090077291A1
公开(公告)日：2009-03-19
申请号：US12276038
申请日：2008-11-21
申请人： Ryan D. Bedwell , Arnaldo R. Cruz , John J. Vaglica , William C. Moyer
发明人： Ryan D. Bedwell , Arnaldo R. Cruz , John J. Vaglica , William C. Moyer
IPC分类号： G06F13/40
CPC分类号： G06F13/364
摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.
摘要翻译：需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。电路（402,417,480）可用于为诸如中断的附加信号提供转向。其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

77. 发明申请

US20080288725A1 METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20080288725A1
公开(公告)日：2008-11-20
申请号：US11748353
申请日：2007-05-14
申请人： William C. Moyer , Michael D. Snyder
发明人： William C. Moyer , Michael D. Snyder
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F11/3656
摘要： A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system.

78. 发明授权

US07415558B2 Communication steering for use in a multi-master shared resource system 有权
标题翻译：用于多主共享资源系统的通信指导
公开(公告)号：US07415558B2
公开(公告)日：2008-08-19
申请号：US11610956
申请日：2006-12-14
申请人： Arnaldo R. Cruz , John J. Vaglica , William C. Moyer , Tuongvu V. Nguyen
发明人： Arnaldo R. Cruz , John J. Vaglica , William C. Moyer , Tuongvu V. Nguyen
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/385 , G06F13/24 , G06F2213/0042
摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.
摘要翻译：需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。电路（402,417,480）可用于为诸如中断的附加信号提供转向。其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

79. 发明授权

US07404019B2 Method and apparatus for endianness control in a data processing system 有权
标题翻译：数据处理系统中字节序控制的方法和装置
公开(公告)号：US07404019B2
公开(公告)日：2008-07-22
申请号：US10857208
申请日：2004-05-26
申请人： William C. Moyer , Michael D. Fitzsimmons
发明人： William C. Moyer , Michael D. Fitzsimmons
IPC分类号： G06F13/12 , G06F3/00 , G06F13/00
CPC分类号： G06F13/4013 , G06F21/85 , G06F2221/2113 , G06F2221/2141
摘要： A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.
摘要翻译：一种用于在数据处理系统中提供字节序控制的方法包括发起访问外围设备的访问，提供与外设相对应的第一字节序列控制，并使用字节序控制来完成访问，以影响在该时间间隔期间传送的信息的字节顺序访问。在一个实施例中，第一字节序列控制覆盖对应于访问的默认字节顺序。默认字节顺序可以由对应于请求当前访问的主机的主字节顺序控制来提供。数据处理系统包括第一总线主机，第一和第二外围设备，对应于与第二外围设备相对应的第一外设和第二终端控制的第一字节序列控制;以及控制电路，其使用第一字节序列控制来控制字节顺序第一个总线主人和第一个外围设备。在一个实施例中，数据处理系统可以包括多个主器件。

80. 发明授权

US07376807B2 Data processing system having address translation bypass and method therefor 有权
标题翻译：具有地址转换旁路的数据处理系统及其方法
公开(公告)号：US07376807B2
公开(公告)日：2008-05-20
申请号：US11360926
申请日：2006-02-23
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0292
摘要： In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and converts the logical address to both a physical address and one or more address attributes. Bypass circuitry that is coupled to the address translator selectively provides the logical address as a translated address of the logical address which was received. In order to speed up the memory address translation, the logical address is selectively provided as the translated address prior to providing the one or more address attributes associated with the logical address.
摘要翻译：在数据处理系统中，包括处理逻辑的处理器执行数据处理。耦合到处理逻辑的地址转换器执行地址转换及其方法。地址转换器接收逻辑地址并将逻辑地址转换为物理地址和一个或多个地址属性。耦合到地址转换器的旁路电路选择性地将逻辑地址提供为所接收的逻辑地址的翻译地址。为了加速存储器地址转换，在提供与逻辑地址相关联的一个或多个地址属性之前，逻辑地址被选择性地提供为转换的地址。

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