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71. 发明申请

US20060172475A1 Ultrathin SOI transistor and method of making the same 失效
标题翻译：超薄SOI晶体管及其制作方法
公开(公告)号：US20060172475A1
公开(公告)日：2006-08-03
申请号：US11050495
申请日：2005-02-01
申请人： Sheng Hsu , Jong-Jan Lee
发明人： Sheng Hsu , Jong-Jan Lee
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/66772 , Y10S438/926
摘要： A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region; depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate; depositing and smoothing a layer of amorphous silicon; selectively etching the sacrificial gate oxide; growing a layer of oxide in the gate region; depositing and smoothing a second layer of amorphous silicon; patterning and etching the second layer of amorphous silicon; implanting ion to form a source region and a drain region; annealing the structure; and depositing a layer of passivation oxide.
摘要翻译：制造超薄SOI存储晶体管的方法包括：制备衬底，包括形成衬底的超薄SOI层; 调整SOI层的阈值电压; 在SOI层上沉积一层氧化硅; 图案化和蚀刻氧化硅层以在栅极区域中形成牺牲氧化物栅极; 沉积氮化硅层并将氮化硅形成用于牺牲氧化物栅极的氮化硅侧壁; 沉积和平滑一层非晶硅; 选择性地蚀刻牺牲栅极氧化物; 在栅极区生长一层氧化物; 沉积和平滑第二层非晶硅; 图案化和蚀刻第二层非晶硅; 注入离子以形成源区和漏区; 退火结构; 并沉积一层钝化氧化物。

72. 发明申请

US20060035451A1 High-density SOI cross-point memory fabricating method 有权
标题翻译：高密度SOI交叉点存储器制造方法
公开(公告)号：US20060035451A1
公开(公告)日：2006-02-16
申请号：US11216680
申请日：2005-08-31
申请人： Sheng Hsu
发明人： Sheng Hsu
IPC分类号： H01L21/4763
CPC分类号： G11C13/003 , G11C13/0007 , G11C2213/31 , G11C2213/72 , G11C2213/77 , G11C2213/78 , H01L27/101 , H01L27/1203 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1226 , H01L45/147 , H01L45/1683
摘要： A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method comprises: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas, and top electrode areas; etching to remove the exposed silicon (Si) surfaces; selectively forming metal sidewalls adjacent the hard mask; filling the memory areas with memory resistor material; removing the hard mask, exposing the underlying Si active device areas; forming an overlying layer of oxide; etching the oxide to form contact holes to the active device areas; forming diodes in the contact holes; and, forming bottom electrode lines overlying the diodes.
摘要翻译：提供了一种用于制造高密度绝缘体上硅（SOI）交叉点存储器阵列和阵列结构的方法。该方法包括：在SOI衬底上选择性地形成硬掩模，限定存储区域，有源器件区域和顶部电极区域; 蚀刻以去除暴露的硅（Si）表面; 选择性地形成邻近硬掩模的金属侧壁; 用存储电阻材料填充存储区; 去除硬掩模，暴露下面的Si有源器件区域; 形成覆盖层的氧化物; 蚀刻氧化物以形成与有源器件区域的接触孔; 在接触孔中形成二极管; 并且形成覆盖二极管的底部电极线。

73. 发明申请

US20050230724A1 3D cross-point memory array with shared connections 审中-公开
标题翻译：具有共享连接的3D交叉点存储阵列
公开(公告)号：US20050230724A1
公开(公告)日：2005-10-20
申请号：US10825830
申请日：2004-04-16
申请人： Sheng Hsu
发明人： Sheng Hsu
IPC分类号： H01L27/10 , G11C11/16 , G11C13/02 , H01L27/24 , H01L31/113 , H01L43/08
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C13/02 , G11C2013/0042 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A 3D cross-point memory array is provided having current sensing devices connected the bit line for reading out the bit value. The 3D cross-point memory array may be configured as multiple resistive memory array layers. Electrodes, either bit lines or word lines, may be connected together between resistive memory array layers.
摘要翻译：提供3D交叉点存储器阵列，其具有连接位线的电流感测装置，用于读出位值。 3D交叉点存储器阵列可以被配置为多个电阻存储器阵列层。电极（位线或字线）可以在电阻性存储器阵列层之间连接在一起。

74. 发明申请

US20050214997A1 Method to form local "silicon-on-nothing" or "silicon-on-insulator" wafers with tensile-strained silicon 有权
标题翻译：用拉伸应变硅形成局部“无硅无硅”或“绝缘体上硅”晶片的方法
公开(公告)号：US20050214997A1
公开(公告)日：2005-09-29
申请号：US10807931
申请日：2004-03-23
申请人： Douglas Tweet , Sheng Hsu , Jer-Shen Maa
发明人： Douglas Tweet , Sheng Hsu , Jer-Shen Maa
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/786
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/78
摘要： A method of forming a substrate for use in IC device fabrication includes preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates; forming a first relaxed SiGe layer on the silicon substrate; forming a first tensile-strained silicon cap on the first relaxed SiGe layer; forming a second relaxed SiGe layer on the first tensile-strained silicon cap; forming a second tensile-strained silicon cap on the second relaxed SiGe layer; and completing an IC device.
摘要翻译：一种形成用于IC器件制造的衬底的方法包括制备硅衬底，其包括用从离子组中取出的离子掺杂体硅（100）衬底，以形成从由n组成的掺杂衬底组中取出的掺杂衬底型掺杂衬底和p型掺杂衬底; 在硅衬底上形成第一弛豫的SiGe层; 在第一松弛SiGe层上形成第一拉伸应变硅帽; 在第一拉伸应变硅帽上形成第二松弛SiGe层; 在第二松弛SiGe层上形成第二拉伸应变硅帽; 并完成IC设备。

75. 发明申请

US20050127403A1 RRAM circuit with temperature compensation 有权
公开(公告)号：US20050127403A1
公开(公告)日：2005-06-16
申请号：US11031321
申请日：2005-01-05
申请人： Sheng Hsu
发明人： Sheng Hsu
IPC分类号： G11C13/02 , G11C7/04 , G11C7/06 , G11C7/14 , G11C11/56 , G11C13/00 , G11C16/02 , H01L27/10 , H01L31/0336
CPC分类号： G11C13/004 , G11C7/04 , G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C2013/0054 , G11C2213/31 , G11C2213/72 , G11C2213/79
摘要： A temperature compensated RRAM sensing circuit to improve the RRAM readability against temperature variations is disclosed. The circuit comprises a temperature dependent element to control the response of a temperature compensated circuit to generate a temperature dependent signal to compensate for the temperature variations of the resistance states of the memory resistors. The temperature dependent element can control the sensing signal supplied to the memory resistor so that the resistance states of the memory resistor are compensated against temperature variations. The temperature dependent element can control the reference signal supplied to the comparison circuit so that the output signal provided by the comparison circuit is compensated against temperature variations. The temperature dependent element is preferably made of the same material and process as the memory resistors.

76. 发明申请

US20050088898A1 Low power flash memory cell and method 审中-公开
标题翻译：低功耗闪存单元和方法
公开(公告)号：US20050088898A1
公开(公告)日：2005-04-28
申请号：US10976596
申请日：2004-10-29
申请人： Sheng Hsu , Yoshi Ono
发明人： Sheng Hsu , Yoshi Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883 , Y10S438/975
摘要： Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.
摘要翻译：闪存单元设置有插入在浮置多晶硅栅极和控制栅极之间的高k材料。在浮置多晶硅栅极和衬底之间插入隧道氧化物。还提供了形成闪存单元的方法，包括在衬底上形成第一多晶硅层。通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部层。然后可以使用CMP工艺将得到的结构平坦化。然后可以在第一多晶硅层上沉积高k电介质层。然后可以在高k电介质层上沉积第三多晶硅层，并使用光致抗蚀剂图案化以形成闪存栅极结构。在图案化期间，蚀刻暴露的第二多晶硅层。在完成去除第二多晶硅层时检测到蚀刻停止。保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。结合形成闪速存储器单元的过程，高k电介质层可以被图案化以允许形成非存储晶体管。

77. 发明申请

US20050070115A1 Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction 失效
标题翻译：通过层压转移在绝缘体上制备松弛硅锗的方法
公开(公告)号：US20050070115A1
公开(公告)日：2005-03-31
申请号：US10677005
申请日：2003-09-30
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas Tweet , Sheng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas Tweet , Sheng Hsu
IPC分类号： H01L21/20 , H01L21/302 , H01L21/461 , H01L21/762
CPC分类号： H01L21/76254
摘要： A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 Å to 1 μm below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括在硅衬底上沉积硅 - 锗层以形成硅/硅 - 锗部分; 在硅 - 锗/硅界面之下的约500埃至1微米处将氢离子注入到硅衬底中; 将硅/硅锗部分接合到绝缘体基板上以形成对联体; 在第一热退火步骤中对联接件进行热退火以分离联接件; 图案化和蚀刻绝缘体上硅部分以去除部分硅和SiGe层; 蚀刻绝缘体上硅部分以除去剩余的硅层; 在第二退火步骤中对绝缘体上硅部分进行热退火以松弛SiGe层; 以及在SiGe层周围沉积一层应变硅。

78. 发明申请

US20070170536A1 Liquid phase epitaxial GOI photodiode with buried high resistivity germanium layer 审中-公开
标题翻译：液相外延GOI光电二极管，埋置高电阻率锗层
公开(公告)号：US20070170536A1
公开(公告)日：2007-07-26
申请号：US11339011
申请日：2006-01-25
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/00
CPC分类号： H01L31/1055 , H01L31/1808 , H01L31/1872 , Y02E10/50
摘要： A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N diode is formed with an n +-doped (n+) mesa, a p+-doped (p+) Ge bottom insulator interface and mesa lateral interface, and a high resistivity Ge layer interposed between the p+ Ge and n+ Ge. A metal electrode is formed overlying a region of the p+ Ge lateral interface, and a transparent electrode is formed overlying the n+ Ge mesa. In one aspect, the method deposits a silicon nitride layer temporary cap overlying the high resistivity Ge layer, and an annealing is performed to epitaxially crystallize the Ge bottom interface and high resistivity Ge layer.
摘要翻译：提供了一种用于制造具有埋置的高电阻率锗（Ge）层的液相外延（LPE）绝缘体锗绝缘体（GOI）光电二极管的器件和相关方法。该方法提供硅（Si）衬底，并且形成具有Si种子存取区域的覆盖Si衬底的底部绝缘体。然后，形成具有n +掺杂（n +）台面，p +掺杂（p +）Ge底部绝缘体界面和台面侧面界面的Ge P-I-N二极管，以及插入在p + Ge和n + Ge之间的高电阻率Ge层。在p + Ge侧面界面的区域上形成金属电极，形成覆盖n + Ge台面的透明电极。在一个方面，该方法沉积覆盖高电阻率Ge层的氮化硅层临时盖，并进行退火以使Ge底界面和高电阻率Ge层外延结晶。

79. 发明申请

US20070167008A1 Nanotip electrode non-volatile memory resistor cell 审中-公开
标题翻译：纳米电极非易失性存储电阻单元
公开(公告)号：US20070167008A1
公开(公告)日：2007-07-19
申请号：US11717818
申请日：2007-03-14
申请人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
发明人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
IPC分类号： H01L21/44
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/147 , H01L45/16 , H01L45/1675
摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
摘要翻译：提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

80. 发明申请

US20070141744A1 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US20070141744A1
公开(公告)日：2007-06-21
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
发明人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the born-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在天然掺杂锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火激活N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

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