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71. 发明授权

US07525360B1 I/O duty cycle and skew control 有权
标题翻译： I / O占空比和偏移控制
公开(公告)号：US07525360B1
公开(公告)日：2009-04-28
申请号：US11735401
申请日：2007-04-13
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K3/017
CPC分类号： G11C7/22 , G06F1/10 , G11C7/1051 , G11C7/1066 , H03K5/04 , H03K5/133 , H03K5/1565 , H03K2005/00058
摘要： Circuits, methods and apparatus are provided to control the duty cycle of a signal. The rising and falling edges of a signal can be delayed independently to provide the selection or tuning of the duty cycle of the signal. Additionally, the delays can be used to reduce skew among both edges of signals being provided or transmitted by a data interface. The delays can be made to not cause a high-Z during a transition of the signal.
摘要翻译：提供电路，方法和装置来控制信号的占空比。可以独立地延迟信号的上升沿和下降沿以提供信号占空比的选择或调谐。此外，延迟可以用于减少由数据接口提供或发送的信号的两个边缘之间的偏差。可以在信号转换期间延迟不会引起高电平。

72. 发明授权

US06314550B1 Cascaded programming with multiple-purpose pins 失效
标题翻译：使用多用途引脚进行级联编程
公开(公告)号：US06314550B1
公开(公告)日：2001-11-06
申请号：US09094226
申请日：1998-06-09
申请人： Bonnie Wang , Chiakang Sung , Khai Huang , Khai Nguyen , Xiaobao Wang
发明人： Bonnie Wang , Chiakang Sung , Khai Huang , Khai Nguyen , Xiaobao Wang
IPC分类号： G06F1710
CPC分类号： H03K19/1732 , G01R31/318555 , G06F11/2273 , H03K19/17744 , H03K19/17748
摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). A technique is to allow a pin to be used for multiple purposes, a dedicated operation during a first mode and for user I/O during other modes. A pin (515) may be used to perform a handshaking function during a configuration mode and user I/O during a normal or user mode. The technique may be used during the cascaded configuration of programmable integrated circuits, and in conjunction with in-system programming.
摘要翻译：通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。一种技术是允许将引脚用于多个目的，在第一模式期间的专用操作以及在其它模式期间的用户I / O。引脚（515）可以在正常或用户模式期间在配置模式和用户I / O期间执行握手功能。该技术可以在可编程集成电路的级联配置期间并结合在系统编程中使用。

73. 发明授权

US07994821B1 Level shifter circuits and methods 有权
标题翻译：电平移位电路和方法
公开(公告)号：US07994821B1
公开(公告)日：2011-08-09
申请号：US12753389
申请日：2010-04-02
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K19/0175
CPC分类号： H03K3/356069
摘要： A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.
摘要翻译：电平移位器电路包括串联耦合的第一和第二晶体管，以及串联耦合的第三和第四晶体管。第四晶体管耦合到第一和第二晶体管之间的第一节点。电平移位器电路还包括串联耦合的第五和第六晶体管，以及串联耦合的第七和第八晶体管。第八晶体管耦合到第五和第六晶体管之间的第二节点。第二和第八晶体管在控制输入端接收第一输入信号。第四和第六晶体管在控制输入端接收第二输入信号。第二输入信号相对于第一输入信号反相。

74. 发明申请

US20070115028A1 Method and apparatus for protecting a circuit during a hot socket condition 有权
标题翻译：在热插座状态下保护电路的方法和装置
公开(公告)号：US20070115028A1
公开(公告)日：2007-05-24
申请号：US11251099
申请日：2005-10-14
申请人： Xiaobao Wang , Khai Nguyen , Chiakang Sung , Bonnie Wang
发明人： Xiaobao Wang , Khai Nguyen , Chiakang Sung , Bonnie Wang
IPC分类号： H03K19/00
CPC分类号： H03K19/00315
摘要： The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.
摘要翻译：本发明的热插座检测电路包括阱偏置电路和三个热插座检测块。如果三个热插座检测块中的任一个的输出是数字高信号，则热插座检测电路的输出是数字高电平信号。数字高电平信号表示存在热插座状况。

75. 发明授权

US06972593B1 Method and apparatus for protecting a circuit during a hot socket condition 失效
标题翻译：在热插座状态下保护电路的方法和装置
公开(公告)号：US06972593B1
公开(公告)日：2005-12-06
申请号：US10635625
申请日：2003-08-05
申请人： Xiaobao Wang , Khai Nguyen , Chiakang Sung , Bonnie Wang
发明人： Xiaobao Wang , Khai Nguyen , Chiakang Sung , Bonnie Wang
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/00315
摘要： The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.
摘要翻译：本发明的热插座检测电路包括阱偏置电路和三个热插座检测块。如果三个热插座检测块中的任一个的输出是数字高信号，则热插座检测电路的输出是数字高电平信号。数字高电平信号表示存在热插座状况。

76. 发明申请

US20050140430A1 Programmable AC current booster for faster edge-rate output in high speed applications 失效
标题翻译：可编程交流电流增压器，用于在高速应用中实现更快的边沿速率输出
公开(公告)号：US20050140430A1
公开(公告)日：2005-06-30
申请号：US10749883
申请日：2003-12-31
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Xiaobao Wang
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Xiaobao Wang
IPC分类号： G05F1/10 , H03K19/00 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01707 , H03K19/0016 , H03K19/01721 , H03K19/018507
摘要： An AC current booster for high speed, high frequency applications having a single-ended output embodiment and a differential output embodiment. The embodiments of the present invention allow bifurcated control of the AC switching rate and the DC state of a given output signal, in order to achieve faster rising and falling edge rates without an undesirable increase in output voltage swing.
摘要翻译：用于具有单端输出实施例和差分输出实施例的高速，高频应用的AC电流增压器。本发明的实施例允许对给定输出信号的AC开关速率和DC状态的分叉控制，以便实现更快的上升和下降沿速率，而不会不期望地增加输出电压摆幅。

77. 发明申请

US20060220703A1 Programmable high speed interface 有权
标题翻译：可编程高速接口
公开(公告)号：US20060220703A1
公开(公告)日：2006-10-05
申请号：US11446483
申请日：2006-06-02
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

78. 发明申请

US20050134332A1 Programmable high speed I/O interface 有权
标题翻译：可编程高速I / O接口
公开(公告)号：US20050134332A1
公开(公告)日：2005-06-23
申请号：US10886015
申请日：2004-07-06
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： G06F3/00 , G06F13/38 , H03K19/0175 , H03K19/173 , H03K19/177 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

79. 发明授权

US06707399B1 Data realignment techniques for serial-to-parallel conversion 有权
标题翻译：用于串行到并行转换的数据重新对准技术
公开(公告)号：US06707399B1
公开(公告)日：2004-03-16
申请号：US10269370
申请日：2002-10-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
IPC分类号： H03M900
CPC分类号： H03M9/00
摘要： Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
摘要翻译：提供了用于调整串并转换器中的数据字节之间边界的技术。串行数据的位被移入第一寄存器。然后，数据字节沿并行信号线移出第一寄存器，进入第二寄存器。从第一寄存器到第二寄存器的并行加载数据的时序确定并行数据字节边界。可以使用负载使能信号来移位并行数据字节之间的边界。可以改变负载使能信号的相位，以将数据字节之间的边界移位一个或多个位。然后可以将并行数据从第二寄存器加载到第三寄存器中。第三寄存器的数据输出信号与核心时钟信号同步，以确保第三寄存器输出的信号的足够的建立和保持时间。

80. 发明授权

US06911923B1 Data realignment techniques for serial-to-parallel conversion 失效
标题翻译：用于串行到并行转换的数据重新对准技术
公开(公告)号：US06911923B1
公开(公告)日：2005-06-28
申请号：US10769733
申请日：2004-01-29
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
IPC分类号： H03M9/00 , G06F1/04 , G06F1/24 , G06F13/12 , G06F13/38
CPC分类号： H03M9/00
摘要： Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
摘要翻译：提供了用于调整串并转换器中的数据字节之间边界的技术。串行数据的位被移入第一寄存器。然后，数据字节沿并行信号线移出第一寄存器，进入第二寄存器。从第一寄存器到第二寄存器的并行加载数据的时序确定并行数据字节边界。可以使用负载使能信号来移位并行数据字节之间的边界。可以改变负载使能信号的相位，以将数据字节之间的边界移位一个或多个位。然后可以将并行数据从第二寄存器加载到第三寄存器中。第三寄存器的数据输出信号与核心时钟信号同步，以确保第三寄存器输出的信号的足够的建立和保持时间。

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