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71. 发明授权

US08874933B2 Instruction set for SHA1 round processing on 128-bit data paths 有权
标题翻译： 128位数据路径SHA1循环处理指令集
公开(公告)号：US08874933B2
公开(公告)日：2014-10-28
申请号：US13631150
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作，逻辑功能在第三个操作数中指定。

72. 发明授权

US08838997B2 Instruction set for message scheduling of SHA256 algorithm 有权
标题翻译： SHA256算法消息调度指令集
公开(公告)号：US08838997B2
公开(公告)日：2014-09-16
申请号：US13631165
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , H04L9/0643 , H04L2209/125
摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.
摘要翻译：处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。

73. 发明申请

US20140095891A1 INSTRUCTION SET FOR SHA1 ROUND PROCESSING ON 128-BIT DATA PATHS 有权
标题翻译： 128位数据表上的SHA1加工指令集
公开(公告)号：US20140095891A1
公开(公告)日：2014-04-03
申请号：US13631150
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作，逻辑功能在第三个操作数中指定。

74. 发明申请

US20160283504A1 Apparatus for Hardware Implementation of Lossless Data Compression 审中-公开
标题翻译：无损数据压缩的硬件实现装置
公开(公告)号：US20160283504A1
公开(公告)日：2016-09-29
申请号：US14671605
申请日：2015-03-27
申请人： James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , Daniel F. Cutter
发明人： James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , Daniel F. Cutter
IPC分类号： G06F17/30
CPC分类号： G06F17/30153 , H03M7/3084 , H03M7/3088 , H03M7/4006
摘要： A processor includes a memory hierarchy, buffer, and a compression module. The compression module includes logic to evaluate a stream of data to be compressed according to a compression scheme, selectively modify a format of the compression scheme based upon a number of literals received, compress a sequence of the data to produce the output data sequence, and send the output data sequence to the memory hierarchy.
摘要翻译：处理器包括存储器层级，缓冲器和压缩模块。压缩模块包括根据压缩方案来评估要压缩的数据流的逻辑，基于所接收的文字数量选择性地修改压缩方案的格式，压缩数据序列以产生输出数据序列;以及将输出数据序列发送到存储器层次结构。

75. 发明授权

US09128698B2 Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction 有权
标题翻译：响应于单个指令执行旋转和异或的系统，设备和方法
公开(公告)号：US09128698B2
公开(公告)日：2015-09-08
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的地操作数和即时价值。

76. 发明申请

US20140189369A1 Instructions Processors, Methods, and Systems to Process Secure Hash Algorithms 有权
标题翻译：指令处理器，方法和系统来处理安全散列算法
公开(公告)号：US20140189369A1
公开(公告)日：2014-07-03
申请号：US13843141
申请日：2013-03-15
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： G06F21/72
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译：方面的方法包括接收指令。该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。该指令指示第二打包数据的第二来源。第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。该方法还包括响应于指令将结果存储在由指令指示的目的地中。结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

77. 发明申请

US20140095844A1 Systems, Apparatuses, and Methods for Performing Rotate and XOR in Response to a Single Instruction 有权
标题翻译：用于对单个指令进行旋转和异或运算的系统，设备和方法
公开(公告)号：US20140095844A1
公开(公告)日：2014-04-03
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的操作数和即时价值。

78. 发明授权

US08953785B2 Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
标题翻译： 128位处理器上的SKEIN256 SHA3算法指令集
公开(公告)号：US08953785B2
公开(公告)日：2015-02-10
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

79. 发明申请

US20140093068A1 INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR 有权
标题翻译： 128位处理器的SKEIN256 SHA3算法指令集
公开(公告)号：US20140093068A1
公开(公告)日：2014-04-03
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

80. 发明申请

US20100161536A1 PATTERN MATCHING 有权
标题翻译：图案匹配
公开(公告)号：US20100161536A1
公开(公告)日：2010-06-24
申请号：US12340360
申请日：2008-12-19
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06N5/02
CPC分类号： H04L63/1416 , G06F21/552
摘要： A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.
摘要翻译：提供了执行模式匹配的方法和装置。该装置包括第一存储器，用于存储表示第一组模式组件的数据，以及第二存储器，用于存储表示第二组模式组件的数据，每个模式组件对应于第一组模式组件的一个或多个组件。第一模式匹配器被配置为在输入流中检测一个或多个模式的第一分量，并且生成指示第一分量的检测的信号。第二模式匹配器被配置为从第一模式匹配器接收信号并且检测该模式集合中的一个或多个模式的第二分量是否紧跟在输入流中的第一分量之后。

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