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71. 发明授权

US07779190B2 Arbitration device for arbitrating among a plurality of master devices, arbitration method, and video processing device including the arbitration device 有权
标题翻译：用于在多个主设备之间进行仲裁的仲裁设备，仲裁方法和包括仲裁设备的视频处理设备
公开(公告)号：US07779190B2
公开(公告)日：2010-08-17
申请号：US12559916
申请日：2009-09-15
申请人： Tetsuji Mochida , Tokuzo Kiyohara , Takashi Yamada
发明人： Tetsuji Mochida , Tokuzo Kiyohara , Takashi Yamada
IPC分类号： G06F13/00
CPC分类号： G06F13/1605
摘要： An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.
摘要翻译：仲裁装置在主设备之间进行仲裁，使得允许每个主设备以预定带宽访问共享存储器，并且仲裁设备允许设计者在已经设置了访问请求的第一时段中设置访问请求通过特定的主设备超出已预先分配的带宽。仲裁设备在跟随第一周期的第二周期中屏蔽来自特定主设备的访问请求。

72. 发明申请

US20090037779A1 EXTERNAL DEVICE ACCESS APPARATUS 有权
标题翻译：外部设备访问设备
公开(公告)号：US20090037779A1
公开(公告)日：2009-02-05
申请号：US11916319
申请日：2006-06-06
申请人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
发明人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F13/385
摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.
摘要翻译：响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到并将写入数据写入由写入地址指定的外部设备。当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

73. 发明授权

US07246202B2 Cache controller, cache control method, and computer system 有权
标题翻译：缓存控制器，缓存控制方法和计算机系统
公开(公告)号：US07246202B2
公开(公告)日：2007-07-17
申请号：US10705413
申请日：2003-11-10
申请人： Hiroyuki Morishita , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Tokuzo Kiyohara
IPC分类号： G06F12/02
CPC分类号： G06F12/0848
摘要： In a computer system that concurrently executes a plurality of tasks, a cache controller eliminates the possibility of the hit rate of one task dropping due to execution of another task. A region managing unit manages a plurality of regions in a cache memory in correspondence with a plurality of tasks. An address receiving unit receives, from a microprocessor, an address of a location in a main memory at which data to be accessed to execute one of the plurality of tasks is stored. A caching unit acquires, if the data to be accessed is not stored in the cache memory, a data block including the data from the main memory, and stores the acquired data block into a region in the cache memory corresponding to the task.
摘要翻译：在同时执行多个任务的计算机系统中，高速缓存控制器消除了由于执行另一个任务而导致一个任务的命中率下降的可能性。区域管理单元对应于多个任务管理高速缓冲存储器中的多个区域。地址接收单元从微处理器接收主存储器中的位置的地址，在该存储器中存储要访问的数据以执行多个任务中的一个。如果要访问的数据未被存储在高速缓冲存储器中，则缓存单元获取包括来自主存储器的数据的数据块，并将所获取的数据块存储在与该任务对应的高速缓冲存储器中的区域中。

74. 发明申请

US20060050593A1 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20060050593A1
公开(公告)日：2006-03-09
申请号：US11204316
申请日：2005-08-16
申请人： Masayuki Toyama , Tokuzo Kiyohara
发明人： Masayuki Toyama , Tokuzo Kiyohara
IPC分类号： G11C8/00
CPC分类号： G11C16/20 , G11C7/1015 , G11C7/1045 , G11C16/06
摘要： A non-volatile memory device is disclosed that can reduce the time required for the initialization process. A non-volatile memory device includes a non-volatile memory array having a plurality of pages. Each page includes a plurality of non-volatile memory cells, a first region for storing data, and a second region for storing control data that is associated with the data of the first region. The non-volatile memory device further includes a read out unit for reading out data from the pages, and a data buffer for temporarily storing data that has been read out from the pages by the read out unit. When reading out the control data, the read out unit reads out the second regions, across a plurality of pages, at one time.
摘要翻译：公开了可以减少初始化过程所需时间的非易失性存储器件。非易失性存储器件包括具有多页的非易失性存储器阵列。每个页面包括多个非易失性存储器单元，用于存储数据的第一区域和用于存储与第一区域的数据相关联的控制数据的第二区域。非易失性存储装置还包括用于从页面读出数据的读出单元和用于临时存储由读出单元从页面读出的数据的数据缓冲器。当读出控制数据时，读出单元一次读出多个页面中的第二区域。

75. 发明授权

US07007138B2 Apparatus, method, and computer program for resource request arbitration 有权
标题翻译：用于资源请求仲裁的装置，方法和计算机程序
公开(公告)号：US07007138B2
公开(公告)日：2006-02-28
申请号：US10413758
申请日：2003-04-15
申请人： Tetsuji Mochida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Tetsuji Mochida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： G06F13/16
CPC分类号： G06F13/1642
摘要： In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.
摘要翻译：在根据本发明的资源请求仲裁设备中，请求屏蔽单元以资源请求设备所需的最小频率对由资源请求设备发出的存储器访问请求REQ进行掩码，并且仲裁单元确认基于优先级的预定静态顺序，请求屏蔽单元未暂停的存储器访问请求RREQ。在该资源请求仲裁装置中，仲裁单元不需要涉及存储器访问请求单元之间的预定优先级顺序以外的任何其他事项，并且基于静态优先级顺序的容易且简单的仲裁系统确保用于确认资源的最小频率请求每个存储器访问请求单元需要。

76. 发明授权

US5694577A Memory conflict buffer for achieving memory disambiguation in compile-time code schedule 失效
标题翻译：用于在编译时代码调度中实现内存消歧的内存冲突缓冲区
公开(公告)号：US5694577A
公开(公告)日：1997-12-02
申请号：US470825
申请日：1995-06-06
申请人： Tokuzo Kiyohara , Wen-mei W. Hwu , William Chen
发明人： Tokuzo Kiyohara , Wen-mei W. Hwu , William Chen
IPC分类号： G06F9/38 , G06F13/00 , G06F12/00
CPC分类号： G06F9/30047 , G06F9/3834 , G06F9/3842
摘要： An apparatus is provided, for use in a computer having a register bank and a device for operand fetch and instruction execution, for monitoring a store address to maintain coherency of preloaded data that is fetched by a load operation and should be effected by at least one subsequent store operation. The apparatus includes an address register bank having entries for holding the address of a load having loaded data which should be affected by at least one subsequent store operation. Each of the entries has associated therewith a pre-load flag and a type field, the pre-load flag being set when the load is executed and reset when there is no need to be affected by a subsequent store operation. The apparatus is further configured to compare the address held in the register bank with the address of a subsequent store operation in consideration of the access type held in the type of field when the pre-load flag is set, and to reset the pre-load flag when special operation which terminate monitoring addresses are detected or the value is updated by non-preload operations. Each of the entries has further associated therewith a retry flag set when the preloaded data is invalid and reloading is required at the point of usage.
摘要翻译：提供了一种用于具有寄存器组和用于操作数获取和指令执行的装置的计算机的装置，用于监视存储地址以维持由加载操作获取的预加载数据的一致性，并且应当由至少一个后续店铺运作。该装置包括地址寄存器组，其具有用于保持具有加载的数据的负载的地址的条目，该地址应受至少一个后续存储操作的影响。每个条目与之相关联的是预加载标志和类型字段，当负载被执行时，预加载标志被设置，并且当不需要受到随后的存储操作的影响时重置。该装置还被配置为在设置预加载标志时，考虑到保持在字段类型中的访问类型，将保存在寄存器组中的地址与后续存储操作的地址进行比较，并重置预加载检测到终止监控地址的特殊操作或通过非预加载操作更新值时的标志。当预加载的数据无效并且在使用时需要重新加载时，每个条目还进一步与其相关联地设置重试标志。

77. 发明授权

US5479620A Control unit modifying micro instructions for one cycle execution 失效
标题翻译：控制单元修改一个周期执行的微指令
公开(公告)号：US5479620A
公开(公告)日：1995-12-26
申请号：US103178
申请日：1993-08-09
申请人： Tokuzo Kiyohara , Kozo Kimura , Takahiro Watanabe
发明人： Tokuzo Kiyohara , Kozo Kimura , Takahiro Watanabe
IPC分类号： G06F9/22 , G06F9/26 , G06F9/318
CPC分类号： G06F9/3017 , G06F9/226 , G06F9/268 , G06F9/328
摘要： A control device includes a memory storing a plurality of micro instructions. A modifying information generator generates modifying information. A modifying unit receives one of the micro instructions and the modifying information from the memory and the modifying information generator respectively. The modifying unit modifies at least part of the one of the micro instructions with the modifying information.
摘要翻译：控制装置包括存储多个微指令的存储器。修改信息生成器生成修改信息。修改单元分别从存储器和修改信息生成器接收微指令之一和修改信息。修改单元利用修改信息修改微指令的至少一部分。

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