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    • 72. 发明授权
    • Digital signal processing circuit for filtering an image signal
vertically
    • 用于垂直滤波图像信号的数字信号处理电路
    • US5495296A
    • 1996-02-27
    • US59561
    • 1993-05-12
    • Shiro DoshoTatsuro Juri
    • Shiro DoshoTatsuro Juri
    • H04N5/14H03H17/00H04N7/00H04N7/46H04N9/804H04N9/808H04N9/87H04N11/04H04N11/16H04N11/22H04N19/00H04N19/423H04N19/426H04N19/59
    • H04N19/59H04N11/22H04N9/8042H04N9/87
    • In order to thin an input signal a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, and a first multiplexer is alternatively switched at every line. A delay circuit memorizes the sum of the two preceding input signals, and the second adder outputs at every other line the sum of image data of a present line and the two preceding lines. To interpolate an input signal, the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output either the input signal or the output of the second multiplexer, and the second multiplexer is alternatively switched to output either the output of the first adder or the output of the delay circuit. Thus, the delay circuit outputs at every other line the sum of the two preceding input signals. Because only one delay circuit is needed the size of the perpendicular thinning/interpolation circuit for an image signal is reduced.
    • 为了使输入信号变薄,第二多路复用器被切换以输出第一加法器的输出,并且第三多路复用器被切换以输出第二加法器的输出,并且第一多路复用器在每一行交替切换。 延迟电路存储前两个输入信号的和,并且第二加法器在每隔一行输出当前行和前两行的图像数据之和。 为了插入输入信号,第二多路复用器被切换以输出延迟电路的输出,第一多路复用器被交替切换以输出第二多路复用器的输入信号或输出,并且第二多路复用器交替切换以输出 第一加法器的输出或延迟电路的输出。 因此,延迟电路在每隔一行输出前面两个输入信号的和。 因为只需要一个延迟电路,所以减小图像信号的垂直细化/插值电路的尺寸。
    • 76. 发明授权
    • Motion estimation device, motion estimation method, motion estimation integrated circuit, and picture coding device
    • 运动估计装置,运动估计方法,运动估计集成电路和图像编码装置
    • US08208541B2
    • 2012-06-26
    • US11695145
    • 2007-04-02
    • Masayasu IguchiTatsuro JuriTakeshi Tanaka
    • Masayasu IguchiTatsuro JuriTakeshi Tanaka
    • H04N7/12
    • H04N19/523H04N19/426H04N19/433H04N19/51H04N19/61
    • Provided is a motion estimation device in which an amount of pixel data transferred from an external frame memory to an internal reference local memory is reduced. By the motion estimation device, it is possible to reduce a memory capacity and a size or processing of a circuit controlling the pixel transfer. In a reference memory control unit and an internal reference memory, a height of a area to be updated is set to L pixels, where L is power of 2, a logical address segments, whose size is suitable for address calculation, are allocated to picture space, and FIFO management is performs. In another application, an assistance memory is added, and another element other than the assistance memory performs the FIFO management for rectangular areas in an image of a conventional width. As a result, the address calculation is simplified, which makes it possible to reduce an embedded circuit for the reference memory control unit and the internal reference memory.
    • 提供了一种运动估计装置,其中从外部帧存储器传输到内部参考本地存储器的像素数据量减少。 通过运动估计装置,可以减少控制像素传送的电路的存储容量和尺寸或处理。 在参考存储器控制单元和内部参考存储器中,要更新的区域的高度被设置为L个像素,其中L是功率2,将适合于地址计算的尺寸的逻辑地址段分配给图像 空间和FIFO管理。 在另一应用中,添加辅助存储器,而辅助存储器以外的其他元件对传统宽度的图像中的矩形区域执行FIFO管理。 结果,地址计算被简化,这使得可以减少用于参考存储器控制单元和内部参考存储器的嵌入式电路。