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71. 发明授权

US07855457B2 Stacked multilayer structure and manufacturing method thereof 有权
标题翻译：堆叠多层结构及其制造方法
公开(公告)号：US07855457B2
公开(公告)日：2010-12-21
申请号：US12163145
申请日：2008-06-27
申请人： Makoto Mizukami , Takeshi Kamigaichi
发明人： Makoto Mizukami , Takeshi Kamigaichi
IPC分类号： H01L23/48
CPC分类号： H01L23/5283 , H01L21/0217 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/76883 , H01L23/5226 , H01L23/528 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L45/06 , H01L2924/0002 , Y10T156/1057 , H01L2924/00
摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
摘要翻译：根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面的触点经由绝缘膜与所述多个导电层绝缘。

72. 发明申请

US20100246255A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：非易失性半导体存储装置及其控制方法
公开(公告)号：US20100246255A1
公开(公告)日：2010-09-30
申请号：US12729626
申请日：2010-03-23
申请人： Yasuhiro SHIINO , Atsuhiro Sato , Takeshi Kamigaichi
发明人： Yasuhiro SHIINO , Atsuhiro Sato , Takeshi Kamigaichi
IPC分类号： G11C16/28
CPC分类号： G11C16/30 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11519 , H01L27/11521
摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.
摘要翻译：非易失性半导体存储装置包括存储单元阵列和外围电路。存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用向第二接触器施加第三电压以改变虚设电池的阈值。

73. 发明授权

US07781822B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07781822B2
公开(公告)日：2010-08-24
申请号：US11246168
申请日：2005-10-11
申请人： Takeshi Kamigaichi , Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Takeshi Kamigaichi , Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L21/28273 , H01L27/11526 , H01L27/11541 , H01L27/11543 , H01L27/11546 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes: a memory cell transistor including a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode; a low voltage transistor constituted by a low voltage gate insulating film, a floating gate electrode, an inter-gate insulating film having an opening, a control gate electrode, a first gate contact plug, and a first metallic salicide film electrically in contact with the first gate contact plug; and a high voltage transistor constituted by a high voltage gate insulating film, a floating gate electrode, an inter-gate insulating film having an opening, a control gate electrode, a second gate contact plug, and a second metallic salicide film electrically in contact with the second gate contact plug. The metallic salicide film is formed only directly beneath the gate contact plug.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括栅极绝缘膜，浮栅电极，栅极间绝缘膜和控制栅电极; 由低电压栅极绝缘膜，浮栅电极，具有开口的栅极间绝缘膜，控制栅电极，第一栅极接触插塞和与第一金属化合物电接触的第一金属硅化物膜构成的低压晶体管第一门接头插头; 以及由高电压栅极绝缘膜，浮栅电极，具有开口的栅极间绝缘膜，控制栅极电极，第二栅极接触插塞和与第二金属化合物电接触的第二金属硅化物膜构成的高压晶体管第二个门接触插头。该金属硅化物膜直接形成在栅极接触塞的正下方。

74. 发明授权

US07352027B2 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
公开(公告)号：US07352027B2
公开(公告)日：2008-04-01
申请号：US11687027
申请日：2007-03-16
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

75. 发明申请

US20070247912A1 SEMICONDUCTOR MEMORY DEVICE IMPROVED IN DATA WRITING 失效
标题翻译：在数据写入中改进的半导体存储器件
公开(公告)号：US20070247912A1
公开(公告)日：2007-10-25
申请号：US11738636
申请日：2007-04-23
申请人： Takeshi Kamigaichi , Riichiro Shirota
发明人： Takeshi Kamigaichi , Riichiro Shirota
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/24 , H01L27/115 , H01L27/11524
摘要： A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a second level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.
摘要翻译：位线由第一和第二NAND单元共享。第一和第二选择晶体管串联在位线和第一NAND单元之间。第三和第四选择晶体管串联在位线和第二NAND单元之间。控制单元将第一和第二信号和位线的电位从第一电平改变到高于第二电平的第二电平，并且在改变第一电平之后将位线的电位从第二电平改变到第一电平信号从第二级到第一级。

76. 发明申请

US20070224736A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD THEREFOR 审中-公开
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20070224736A1
公开(公告)日：2007-09-27
申请号：US11756300
申请日：2007-05-31
申请人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L21/8239
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/4236 , H01L29/7881
摘要： A fabrication method for a nonvolatile semiconductor memory forming gate insulating films for a memory cell transistor and a select gate transistor on a semiconductor substrate, forming a floating gate for the memory cell transistor and a gate electrode for the select gate transistor, forming a cap insulating film for the floating gate, forming a device isolating region, depositing an inter-gate insulating film between the floating gate and control gates for the memory cell transistor, forming a control gate for the memory cell transistor and a gate interconnect for the select gate transistor, forming a salicide control insulating film across the entire surface of the device, and selectively removing the salicide control insulating film on the control gate and on an exposed surface of the semiconductor substrate.
摘要翻译：一种在半导体衬底上形成用于存储单元晶体管和选择栅极晶体管的栅极绝缘膜的非易失性半导体存储器的制造方法，形成用于存储单元晶体管的浮动栅极和用于选择栅极晶体管的栅电极，形成绝缘帽形成器件隔离区域，在浮置栅极和存储单元晶体管的控制栅极之间沉积栅极间绝缘膜，形成用于存储单元晶体管的控制栅极和用于选择栅极晶体管的栅极互连在整个装置的表面上形成一个自对准硅化物控制绝缘膜，并选择性地去除控制栅极上和该半导体衬底的暴露表面上的自对准硅化物控制绝缘膜。

77. 发明申请

US20070164343A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
公开(公告)号：US20070164343A1
公开(公告)日：2007-07-19
申请号：US11687027
申请日：2007-03-16
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

78. 发明授权

US07244984B2 Nonvolatile semiconductor memory including two memory cell columns sharing a single bit line 失效
标题翻译：包括共享单个位线的两个存储单元列的非易失性半导体存储器
公开(公告)号：US07244984B2
公开(公告)日：2007-07-17
申请号：US10892445
申请日：2004-07-16
申请人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/4236 , H01L29/7881
摘要： This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.
摘要翻译：该非易失性半导体存储器包括：具有与浮动栅极串联连接的存储单元晶体管的第一和第二存储单元列以及位于该浮置栅极两侧的第一和第二控制栅极; 连接在第一存储单元列和位线之间的第一选择栅晶体管; 连接在第二存储单元列和位线之间的第二选择栅晶体管; 以及分别连接在第一存储单元列和源极线之间以及第二存储单元列和源极线之间的第三选择栅极晶体管。

79. 发明申请

US20070018226A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20070018226A1
公开(公告)日：2007-01-25
申请号：US11246168
申请日：2005-10-11
申请人： Takeshi Kamigaichi , Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Takeshi Kamigaichi , Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/105 , H01L21/28273 , H01L27/11526 , H01L27/11541 , H01L27/11543 , H01L27/11546 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes: a memory cell transistor including a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode; a low voltage transistor constituted by a low voltage gate insulating film, a floating gate electrode, an inter-gate insulating film having an opening, a control gate electrode, a first gate contact plug, and a first metallic salicide film electrically in contact with the first gate contact plug; and a high voltage transistor constituted by a high voltage gate insulating film, a floating gate electrode, an inter-gate insulating film having an opening, a control gate electrode, a second gate contact plug, and a second metallic salicide film electrically in contact with the second gate contact plug. The metallic salicide film is formed only directly beneath the gate contact plug.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括栅极绝缘膜，浮栅电极，栅极间绝缘膜和控制栅电极; 由低电压栅极绝缘膜，浮栅电极，具有开口的栅极间绝缘膜，控制栅电极，第一栅极接触插塞和与第一金属化合物电接触的第一金属硅化物膜构成的低压晶体管第一门接头插头; 以及由高电压栅极绝缘膜，浮栅电极，具有开口的栅极间绝缘膜，控制栅极电极，第二栅极接触插塞和与第二金属硅化物膜电接触的第二金属硅化物膜构成的高压晶体管第二个门接触插头。该金属硅化物膜直接形成在栅极接触塞的正下方。

80. 发明申请

US20060267143A1 Semiconductor integrated circuit device and manufacturing method thereof 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060267143A1
公开(公告)日：2006-11-30
申请号：US11346292
申请日：2006-02-03
申请人： Kikuko Sugimae , Takeshi Kamigaichi
发明人： Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531
摘要： A semiconductor integrated circuit device includes an element isolation region which is formed in a semiconductor substrate to isolate an element region of the semiconductor substrate, memory cells having floating gates and formed on the element region, and resistor elements formed on the element region. The floating gate has a laminated structure containing a plurality of conductive films. The resistor element has a contact portion for connection with a wiring and a resistor portion acting as a resistor. The resistor portion has a laminated structure having at least one of the plurality of conductive films and an insulating material having a selective etching ratio with respect to the semiconductor substrate.
摘要翻译：半导体集成电路器件包括形成在半导体衬底中以隔离半导体衬底的元件区域的元件隔离区域，具有形成在元件区域上的浮动栅极的存储单元以及形成在元件区域上的电阻器元件。浮栅具有包含多个导电膜的层叠结构。电阻元件具有用于与布线连接的接触部分和用作电阻器的电阻部分。电阻部分具有层叠结构，其具有多个导电膜中的至少一个和相对于半导体衬底具有选择性蚀刻比的绝缘材料。

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