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71. 发明授权

US4476562A Method of error correction 失效
标题翻译：纠错方法
公开(公告)号：US4476562A
公开(公告)日：1984-10-09
申请号：US536824
申请日：1983-09-28
申请人： Yoichiro Sako , Kentaro Odaka
发明人： Yoichiro Sako , Kentaro Odaka
IPC分类号： H03M13/00 , G11B20/18 , H03M13/15 , G06F11/10
CPC分类号： H03M13/15 , G11B20/1809 , H03M13/151
摘要： Error detection and correction method and apparatus for use with digital data signals, which have been coded using cross-interleaving error correction codes with added check words prior to transmission, employ a plurality (k) of syndrome word signals S.sub.O. . . S.sub.k-1) that are generated by multiplying one block (V.sup.t) of the received digital data signals with a parity check matrix, in which each element of one predetermined row is a function of a root of an irreducible polynomial on Galois field GF (2), the syndromes are used to obtain a set of constant word signals (A, B, and C). Error detection and correction is based on these developed syndrome word and constant word signals, in which if selected syndrome word and constant word signal levels are equal to zero, there is no error word declared; if selected ones of the syndrome word and constant word signal levels are equal to zero and selected other signal levels are not equal to zero, then one error word is declared and error correction is performed by calculation of the syndrome word signals which have been determined to be the equivalent of error pattern signals; and if selected constant word signal levels are not equal to zero, additional constant word signals (D, E) are generated and an error location equation is solved to detect the error locations (i, j) and the two word errors are corrected based on the syndrome/error pattern relationship. Up to two word errors in one error correcting block can be detected and corrected and three word errors or four word errors can be corrected if the error locations are known.
摘要翻译：在数据数据信号中使用的错误检测和校正方法和装置，其使用在发送之前具有相加校验字的交叉交错纠错码进行编码，采用多个（k）个校正子信号SO。。。通过将接收的数字数据信号的一个块（Vt）与奇偶校验矩阵相乘而产生的，其中一个预定行的每个元素是伽罗瓦域GF（2）上的不可约多项式的根的函数），使用综合来获得一组恒定字信号（A，B和C）。误差检测和校正是基于这些开发的校正字和常数字信号，其中如果选择的校正子字和常数字信号电平等于零，则没有声明的错误字; 如果校正子字和常数字信号电平中的选定的等于零并且所选择的其他信号电平不等于零，则声明一个错误字，并且通过计算确定为相当于错误模式信号; 并且如果所选择的常数字信号电平不等于零，则产生额外的常数字信号（D，E），并且解决误差位置方程以检测误差位置（i，j），并且基于综合征/错误模式关系。如果错误位置已知，则可以检测和纠正一个纠错块中的两个字错误，并纠正三个字错误或四个字错误。

72. 发明授权

US4473887A Processing circuit for operating on elements of a Galois field 失效
标题翻译：用于对伽罗瓦域的元件进行操作的处理电路
公开(公告)号：US4473887A
公开(公告)日：1984-09-25
申请号：US360205
申请日：1982-03-22
申请人： Kentaro Odaka
发明人： Kentaro Odaka
IPC分类号： G06F11/10 , G06F1/03 , G06F7/00 , G06F7/72 , G06F17/10 , G11B20/18 , H03M13/00 , H03M13/15 , G06F7/52
CPC分类号： H03M13/15 , G06F7/724 , G06F7/726 , G11B20/1809 , G06F1/0307
摘要： An operating circuit operates on digital data words to form products or quotients of the quantities represented by the digital data words. The data words are considered as elements .alpha..sup.i of a Galois field GF(2.sup.m) where each element is a power .alpha..sup.i of an irreducible root. The data words are input into a conversion ROM which in response provides the corresponding exponents i as an output. These exponents i, j are additively combined to form a sum (i+j) or difference (i-j), and this is applied to a reverse conversion ROM. The latter then provides, as an output data word, an element .alpha..sup.i+j or .alpha..sup.i-j which is the product or quotient, respectively, of the input data words. A provision can be incorporated to compensate for division by a zero element. This circuit finds favorable application in error correction of a transmitted or recorded digital signal.
摘要翻译：操作电路对数字数据字进行操作以形成由数字数据字表示的量的乘积或商。数据字被认为是伽罗瓦域GF（2m）的元素αi，其中每个元素是不可约根的幂αi。数据字被输入到转换ROM中，转换ROM响应提供相应的指数i作为输出。这些指数i，j被相加地组合以形成和（i + j）或差（i-j），并且这被应用于反向转换ROM。然后，后者分别作为输出数据字提供作为输入数据字的乘积或商的元素αi + j或αi-j。可以纳入一项条款，以补偿零元素的划分。该电路在发送或记录的数字信号的纠错中有较好的应用。

73. 发明授权

US4451921A PCM Signal processing circuit 失效
标题翻译： PCM信号处理电路
公开(公告)号：US4451921A
公开(公告)日：1984-05-29
申请号：US289970
申请日：1981-08-04
申请人： Kentaro Odaka
发明人： Kentaro Odaka
IPC分类号： H04B1/10 , G11B20/18 , G11B27/031 , H04B14/04 , G06F11/00 , G06F11/26
CPC分类号： G11B27/031 , G11B20/1806 , G11B20/1876
摘要： A pulse code modulation signal processing circuit, for example, for an audio recording and reproducing apparatus to be used with a video tape recorder wherein errors occurring in the pulse code modulated signals are detected by serially providing incoming pulse code modulated data words to serially connected shift registers which are, respectively, adapted to store one word. The outputs of the first and third register are added and divided by two and this divided output is added with the inverted output of the second shift register and the results are compared with a reference signal to determine a one or zero. The one indicates that there is an error in one of the words and the zero indicates that there is no error. The ones or zeros from the comparing circuit are stored in three serially connected one bit shift registers which are timed with the data receiving shift registers and if a one occurs in any of the second shift registers an interpolation circuit is utilized to interpolate the output serial connected words from the first three shift registers. When the second shift register does not contain any ones, but contain only zeros, then it is known that the signals in the first three serially connected shift registers are correct.
摘要翻译：脉冲编码调制信号处理电路，例如用于与磁带录像机一起使用的音频记录和再现装置，其中通过串行提供输入的脉冲编码调制数据字来串行连接的移位来检测脉冲编码调制信号中出现的错误寄存器分别适于存储一个字。将第一和第三寄存器的输出相加并除以2，该分频输出与第二移位寄存器的反相输出相加，并将结果与参考信号进行比较以确定一个或零。一个表示在其中一个单词中有错误，零表示没有错误。来自比较电路的零或零存储在与数据接收移位寄存器定时的三个串行连接的一位移位寄存器中，并且如果在任何第二移位寄存器中发生一个移位寄存器，则使用内插电路来内插输出串行连接来自前三个移位寄存器的单词。当第二移位寄存器不包含任何一个，但只包含零时，就知道前3个串行移位寄存器中的信号是正确的。

74. 发明授权

US4449061A Wave-shaping circuit for digital signal 失效
标题翻译：数字信号波形整形电路
公开(公告)号：US4449061A
公开(公告)日：1984-05-15
申请号：US273729
申请日：1981-06-15
申请人： Nobuyuki Yasuda , Kentaro Odaka
发明人： Nobuyuki Yasuda , Kentaro Odaka
IPC分类号： G11B5/09 , G11B20/10 , H03K5/08 , H04L25/03 , H04L25/04
CPC分类号： G11B20/10527 , H03K5/088
摘要： A wave-shaping circuit for digital signal includes a slice or clipping circuit for slicing or clipping an input digital signal with a predetermined threshold level; a detecting circuit for detecting the pulse widths of high and low level portions of the sliced digital signal; and a control circuit which lowers the threshold level of the slice circuit, when the pulse width of the high level portion of the digital signal is short with respect to the normalized digital signal, and rises the threshold level of the slice circuit, when the pulse width of the low level portion of the digital signal is short with respect to the normalized digital signal.
摘要翻译：用于数字信号的波形整形电路包括用于以预定阈值电平对输入数字信号进行限幅或削波的切片或削波电路; 用于检测分片数字信号的高电平和低电平部分的脉冲宽度的检测电路; 以及控制电路，当数字信号的高电平部分的脉冲宽度相对于归一化的数字信号短时，降低限幅电路的阈值电平，并且当脉冲相对于归一化的数字信号，数字信号的低电平部分的宽度较短。

75. 发明授权

US4438464A Method for editing of PCM signal and apparatus thereof 失效
标题翻译： PCM信号编辑方法及其装置
公开(公告)号：US4438464A
公开(公告)日：1984-03-20
申请号：US324139
申请日：1981-11-23
申请人： Kentaro Odaka
发明人： Kentaro Odaka
IPC分类号： G11B20/18 , G11B27/02 , G11B27/032 , G11B5/00
CPC分类号： G11B27/02 , G11B20/1809 , G11B27/032
摘要： A method for editing a PCM signal in which a first redundant code series is added to a PCM word series in a first arranging state (alignment) and a second redundant code series is added to the PCM word series and the first redundant code series in a second arranging state (alignment) after being interleaved. When desired data is intended to be edited from a master tape on which such PCM data as set forth was recorded, the first PCM data as well as the first and second redundant code series are supplied to a recording encoder so as to restrict an initial value of an interleaving circuit provided in the recording encoder to the same value as that already recorded. Also, an editing apparatus for implementing this process is described.
摘要翻译：一种用于编辑PCM信号的方法，其中在第一布置状态（对齐）和第二冗余码序列中将第一冗余码序列添加到PCM字序列中，将PCM字串和第一冗余码序列相加交错后的第二排列状态（对准）。当想要从记录有所述PCM数据的主磁带编辑期望的数据时，将第一PCM数据以及第一和第二冗余码序列提供给记录编码器，以限制初始值在记录编码器中提供的交错电路与已经记录的相同的值。此外，描述了用于实现该处理的编辑装置。

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