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71. 发明授权

US08343840B2 Blocking dielectric engineered charge trapping memory cell with high speed erase 有权
标题翻译：阻塞具有高速擦除的介电工程电荷捕获存储单元
公开(公告)号：US08343840B2
公开(公告)日：2013-01-01
申请号：US12763006
申请日：2010-04-19
申请人： Sheng-Chih Lai , Hang-Ting Lue , Chien-Wei Liao
发明人： Sheng-Chih Lai , Hang-Ting Lue , Chien-Wei Liao
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28282 , H01L27/11568 , H01L29/513 , H01L29/792
摘要： A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.
摘要翻译：带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括通道由工程隧道电介质。

72. 发明申请

US20120220111A1 INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN 审中-公开
标题翻译：注射方法与肖特源/排水
公开(公告)号：US20120220111A1
公开(公告)日：2012-08-30
申请号：US13463264
申请日：2012-05-03
申请人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
发明人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L21/04
CPC分类号： H01L29/665 , G11C16/0408 , H01L29/40117 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.
摘要翻译：描述了具有肖特基源和漏极的非易失性存储单元的注入方法。载流子注入效率由硅化物和硅的界面特性控制。通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

73. 发明授权

US08252654B2 Method for manufacturing memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US08252654B2
公开(公告)日：2012-08-28
申请号：US12942312
申请日：2010-11-09
申请人： Tzu-Hsuan Hsu , Hang-Ting Lue
发明人： Tzu-Hsuan Hsu , Hang-Ting Lue
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/66833 , H01L29/792
摘要： In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.
摘要翻译：在存储单元的制造方法中，设置有基板。在基板的表面附近形成具有第一导电类型的掺杂区域。去除衬底的一部分以在衬底中限定多个鳍结构。在翅片结构之间形成多个隔离结构。隔离结构的表面低于翅片结构的表面。栅极结构形成在衬底上并跨越翅片结构。栅极结构包括跨过鳍结构的栅极和位于鳍结构和栅极之间的电荷存储结构。源极/漏极区域由栅极结构暴露的鳍状结构中的第二导电类型形成，并且第一导电类型不同于第二导电类型。

74. 发明申请

US20120182807A1 Three-Dimensional Stacked and-Type Flash Memory Structure and Methods of Manufacturing and Operating the Same Hydride 有权
标题翻译：三维堆叠型闪存结构及制造和操作相同氢化物的方法
公开(公告)号：US20120182807A1
公开(公告)日：2012-07-19
申请号：US13008384
申请日：2011-01-18
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C11/34 , H01L21/336 , H01L29/792
CPC分类号： H01L27/11556 , G11C8/16 , G11C16/0416 , H01L27/11524
摘要： A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.
摘要翻译： 3D堆叠的AND型闪速存储器结构包括以三维阵列布置的多个存储单元的水平面，并且每个水平面包括交替布置的多个字线和几个电荷俘获多层，并且相邻的字线与每个其他每个电荷捕获多层介于其间; 交替布置并垂直于水平面布置的多组位线和源极线; 以及交替布置并且垂直于水平面布置的多组绝缘柱和一组绝缘柱，其中一组通道夹在相邻的位线组和源极线之间。

75. 发明申请

US20120181684A1 Semiconductor Structure and Method for Manufacturing the Same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120181684A1
公开(公告)日：2012-07-19
申请号：US13009502
申请日：2011-01-19
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao
IPC分类号： H01L23/48 , H01L21/31
CPC分类号： H01L23/485 , H01L24/64 , H01L27/11578 , H01L29/4234 , H01L29/792
摘要： A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.
摘要翻译：提供半导体结构及其制造方法。该方法包括以下步骤。在基板上形成第一含硅导电材料。在第一含硅导电材料上形成第二含硅导电材料。第一含硅导电材料和第二含硅导电材料具有不同的掺杂条件。第一含硅导电材料和第二含硅导电材料被热氧化，以将第一含硅导电材料完全转变成绝缘氧化物结构，第二含硅导电材料变成含硅导电结构，绝缘氧化物层。

76. 发明授权

US08208279B2 Integrated circuit self aligned 3D memory array and manufacturing method 有权
标题翻译：集成电路自对准3D存储阵列及制造方法
公开(公告)号：US08208279B2
公开(公告)日：2012-06-26
申请号：US12692798
申请日：2010-01-25
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/02 , H01L27/0688 , H01L27/101 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.
摘要翻译： 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，排列成可通过解码电路耦合到读出放大器的位线。导电材料条具有在脊形叠层的侧面上的侧表面。布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。导线符合堆叠的表面。存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。存储器元件是可编程的，如抗熔丝或电荷捕获结构。 3D存储器仅使用两层用于多层的关键掩模。

77. 发明申请

US20120051137A1 Memory Architecture of 3D Array With Diode In Memory String 有权
标题翻译：内存字符串中二极管的3D阵列的内存架构
公开(公告)号：US20120051137A1
公开(公告)日：2012-03-01
申请号：US13011717
申请日：2011-01-21
申请人： Chun-Hsiung Hung , Shin-Jang Shen , Hang-Ting Lue
发明人： Chun-Hsiung Hung , Shin-Jang Shen , Hang-Ting Lue
IPC分类号： G11C16/04 , H01L27/08 , G11C16/10
CPC分类号： H01L27/11578 , G11C16/0466 , G11C16/0483 , G11C16/10 , H01L21/76838 , H01L27/1021 , H01L27/11582
摘要： A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
摘要翻译： 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。导电材料条具有在脊形叠层的侧面上的侧表面。布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。

78. 发明授权

US08023328B2 Memory device with charge trapping layer 有权
标题翻译：具有电荷捕获层的存储器件
公开(公告)号：US08023328B2
公开(公告)日：2011-09-20
申请号：US12338751
申请日：2008-12-18
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/3468
摘要： A memory device is disclosed. The memory device includes a charge trapping layer, and a substrate underlying the charge trapping layer. The carriers are introduced into the charge trapping layer to make a first memory state, for example, when a positive voltage is applied to the gate. At least one of the carriers is released from the charge trapping layer to make a second memory state, for example, when a negative voltage is applied to the gate.
摘要翻译：公开了一种存储器件。存储器件包括电荷俘获层和电荷陷阱层下面的衬底。载流子被引入电荷俘获层以形成第一存储器状态，例如当正电压施加到栅极时。至少一个载体从电荷捕获层释放以形成第二存储器状态，例如当向栅极施加负电压时。

79. 发明授权

US07924626B2 Efficient erase algorithm for SONOS-type NAND flash 有权
标题翻译： SONOS型NAND闪存的高效擦除算法
公开(公告)号：US07924626B2
公开(公告)日：2011-04-12
申请号：US12625438
申请日：2009-11-24
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages.
摘要翻译：用于操作如本文所述的介电电荷捕获存储器单元的方法包括将预定电压从栅极施加到存储器单元的衬底预定时间段以减小存储器单元的阈值电压。该方法包括将来自栅极的电压序列施加到存储器单元的衬底，以进一步降低存储器单元的阈值电压，其中电压序列中的后续电压具有比栅极至衬底的量级小的电压序列中的先前电压。

80. 发明申请

US20110080766A1 Resistive Memory Device and Manufacturing Method Thereof and Operating Method Thereof 有权
标题翻译：电阻式存储器件及其制造方法及其操作方法
公开(公告)号：US20110080766A1
公开(公告)日：2011-04-07
申请号：US12574938
申请日：2009-10-07
申请人： Kuo-Pin Chang , Hang-Ting Lue , Cheng-Hung Tsai
发明人： Kuo-Pin Chang , Hang-Ting Lue , Cheng-Hung Tsai
IPC分类号： H01L45/00 , H01L21/28 , G11C11/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/0011 , H01L27/24 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/16
摘要： A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.
摘要翻译：制造电阻式存储器的方法包括以下步骤：在衬底中形成具有第一杂质扩散层，第二杂质扩散层和第三杂质扩散层的第一注入层叠结构; 蚀刻至少所述第一注入层叠结构以形成多个第二注入层叠结构，其中所述第一杂质扩散层为第一信号线; 在所述第二植入层叠结构之间形成多个第一绝缘层; 蚀刻所述第二注入层叠结构以形成多个第三注入层叠结构，其中所述第一信号线未被蚀刻; 在所述第三植入层叠结构之间形成多个第二绝缘层; 形成电耦合到所述第三杂质扩散层的多个存储材料层; 以及形成垂直于第一信号线的多个第二信号线，并电耦合到存储材料层。

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