专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US06584576B1 Memory system using complementary delay elements to reduce rambus module timing skew 有权
标题翻译：使用互补延迟元件的存储器系统来减少Rambus模块的定时偏移
公开(公告)号：US06584576B1
公开(公告)日：2003-06-24
申请号：US09439792
申请日：1999-11-12
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： H04L700
CPC分类号： G06F13/4239
摘要： An improvement in a Rambus memory system of the type used in personal computers. On a module level, each RIMM (Rambus Interface Memory Module) includes a positive and a negative module time delay element on the CTM (clock to master) clock line. On a system level, where a motherboard has a plurality of RIMMs coupled to a chipset (i.e. memory controller), a positive or negative system time delay element is placed on the CFM (clock from master line). By virtue of the module and system time delay elements, the clock timing can be adjusted from the data timing, whereby the overall TQ (timing skew between clock and data) can be advantageously reduced to allow more RIMMs to be placed on the same motherboard. What is more, the module and system delays also improve timing margins on the standard Rambus channel so as to increase the robustness of a conventional Rambus system.
摘要翻译：在个人电脑中使用的Rambus存储系统的改进。在模块级别，每个RIMM（Rambus接口存储器模块）在CTM（时钟到主机）时钟线上包括一个正负模块时间延迟元件。在系统级别，主板具有耦合到芯片组（即，存储器控制器）的多个RIMM，在CFM（来自主线的时钟）上放置正或负系统时间延迟元件。通过模块和系统时间延迟元件，可以从数据定时调整时钟定时，从而可以有利地减少总体TQ（时钟和数据之间的时序偏差），以允许更多的RIMM被放置在相同的主板上。此外，模块和系统延迟也提高了标准Rambus通道的时序裕度，从而增加了常规Rambus系统的鲁棒性。

72. 发明授权

US06396841B1 Dual-speed stackable repeater with internal bridge for cascading or speed-linking 失效
标题翻译：双速可堆叠中继器，具有用于级联或速度链接的内部桥
公开(公告)号：US06396841B1
公开(公告)日：2002-05-28
申请号：US09103337
申请日：1998-06-23
申请人： Ramon S. Co , Daniel Hsu
发明人： Ramon S. Co , Daniel Hsu
IPC分类号： H04L1228
CPC分类号： H04L12/4625 , H04L12/44 , H04L69/18
摘要： Repeater units in a stack are identical. Each repeater unit has an internal repeater and an internal bridge. The repeater stack is dual-speed, with each repeater connecting to a 10 Mbps (10M) backplane bus and to a 100 Mbps (100M) backplane bus in the stack's chassis. The internal repeater has a 10M repeater circuit that connects 10M ports to the 10M bus, and a 100M repeater circuit that connects 100M ports to the 100M bus. Ports are configured for either 10M or 100M operation. Data from 10M ports is repeated to all other 10M ports and to the 10M bus, but not to 100M ports or the 100M bus. Instead, a 10M port is connected to the internal bridge, which is also connected to a 100M port. The internal bridge stores and forwards packets to and from the 10M port and the 100M port. Only one internal bridge in the stack is configured to link the 10M and 100M ports. Other internal bridges are configured to connect a cascading port to the internal repeater. The cascading port is buffered by the internal bridge. This buffering allows external repeaters to be cascaded without regard to the repeater limit. Repeater units in the stack can be automatically configured to enable only the first internal bridge for 10/100M linking, with the other repeater units'internal bridges configured for cascading.
摘要翻译：堆叠中的中继器单元是相同的。每个中继器单元具有内部中继器和内部桥接器。中继器堆栈是双速的，每个中继器连接到堆叠机箱中的10 Mbps（10M）背板总线和100 Mbps（100M）背板总线。内部中继器具有10M中继器电路，将10M端口连接到10M总线，以及一个100M中继器电路，将100M端口连接到100M总线。端口配置为10M或100M操作。来自10M端口的数据重复到所有其他10M端口和10M总线，而不是100M端口或100M总线。而是将一个10M端口连接到内部网桥，该网桥也连接到100M端口。内部桥存储和转发数据包到10M端口和100M端口。堆叠中只有一个内部网桥被配置为链接10M和100M端口。其他内部网桥被配置为将级联端口连接到内部中继器。级联端口由内部桥缓冲。这种缓冲允许外部中继器级联，而不考虑中继器限制。堆叠中的中继器单元可以自动配置为仅启用10 / 100M链接的第一个内部桥，其他中继器单元的内部桥接配置为级联。

73. 发明授权

US06357023B1 Connector assembly for testing memory modules from the solder-side of a PC motherboard with forced hot air 有权
标题翻译：连接器组件，用于通过强制热空气从PC主板的焊料侧测试内存模块
公开(公告)号：US06357023B1
公开(公告)日：2002-03-12
申请号：US09702017
申请日：2000-10-30
申请人： Ramon S. Co , Steve Si-Yu Chen , Fred Yen Kong , Thang Nguyen
发明人： Ramon S. Co , Steve Si-Yu Chen , Fred Yen Kong , Thang Nguyen
IPC分类号： H02H305
CPC分类号： G01R31/01 , G01R31/31713 , G01R31/31905 , G11C5/04 , G11C29/028 , G11C29/56 , G11C29/56016 , G11C2029/5004 , H05K1/141
摘要： Memory modules are tested using a test assembly with a personal computer (PC) motherboard. The motherboard is mounted upside-down with its solder-side up to a metal plate using standoffs. A memory-module socket on the motherboard is removed. An opening is made in the metal plate above the removed socket. A well is attached to the metal plate at the opening. The well supports a test adaptor board below the metal plate so that the test adaptor board has a closer spacing to the motherboard than does the metal plate. The test adaptor board has a test socket that receives a module being tested. Pins from the test adaptor board are plugged into the holes of the removed socket on the motherboard, but mounted on the reverse, solder side of the motherboard rather than the component side. The cables, components, and expansion boards of the motherboards are hidden below the metal plate and motherboard, and can be cooled without cooling the memory module in the test socket. A top plate or air guide can be added above the metal plate to blow hot air on the memory module being tested in the test socket, while the cooling air is blown on the motherboard.
摘要翻译：使用具有个人计算机（PC）主板的测试组件测试内存模块。主板使用对接方式将其焊接侧倒置到金属板上。主板上的内存模块插槽被拆除。在拆卸的插座上方的金属板上形成一个开口。一个井在开口处附着在金属板上。该井在金属板下面支撑测试适配器板，使得测试适配器板与母板相比，具有比金属板更近的间隔。测试适配器板有一个测试插座，可以接收正在测试的模块。来自测试适配器板的引脚插入主板上拆卸的插槽的孔中，但安装在母板的反面焊接面，而不是组件侧。主板的电缆，组件和扩展板隐藏在金属板和主板下面，可以在不对测试插座内的内存模块进行冷却的情况下进行冷却。可以在金属板上方添加顶板或空气引导件，以将吹入测试插座中的被测试的存储器模块上的热空气吹到主板上。

74. 发明授权

US5602882A Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer 失效
标题翻译：数字抖动衰减器采用多相时钟选择和自动定心弹性缓冲器
公开(公告)号：US5602882A
公开(公告)日：1997-02-11
申请号：US588902
申请日：1996-01-19
申请人： Ramon S. Co , Lance K. Lee
发明人： Ramon S. Co , Lance K. Lee
IPC分类号： H04J3/06 , H04L7/033 , H04L12/42 , H04L7/00
CPC分类号： H04J3/0626 , H04L12/422 , H04J3/0632
摘要： A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
摘要翻译：抖动衰减器接收从输入数据流提取的数据和接收时钟。生成发送时钟用于重发数据。发送时钟的抖动小于接收时钟，但平均频率相同。需要一个弹性缓冲区或FIFO来缓冲数据。接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。一系列多相时钟用于产生传输时钟。多相时钟都具有相同的频率，但相位偏移。在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。计数器由相位比较器递增或递减。相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟更先进的阶段。因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。

75. 发明授权

US5502750A Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network 失效
标题翻译：数字抖动衰减器采用多相时钟选择和自动定心弹性缓冲区，用于令牌环网络
公开(公告)号：US5502750A
公开(公告)日：1996-03-26
申请号：US259910
申请日：1994-06-15
申请人： Ramon S. Co , Lance K. Lee
发明人： Ramon S. Co , Lance K. Lee
IPC分类号： H04J3/06 , H04L7/033 , H04L12/42 , H04L7/00
CPC分类号： H04J3/0626 , H04L12/422 , H04J3/0632
摘要： A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
摘要翻译：抖动衰减器接收从输入数据流提取的数据和接收时钟。生成发送时钟用于重发数据。发送时钟的抖动小于接收时钟，但平均频率相同。需要一个弹性缓冲区或FIFO来缓冲数据。接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。一系列多相时钟用于产生传输时钟。多相时钟都具有相同的频率，但相位偏移。在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。计数器由相位比较器递增或递减。相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟更先进的阶段。因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。

76. 发明授权

US4706244A Frequency multiplexed telephone system 失效
标题翻译：频率复用电话系统
公开(公告)号：US4706244A
公开(公告)日：1987-11-10
申请号：US692597
申请日：1985-01-15
申请人： George A. Watson , Ramon S. Co , James L. Fuhrman , Frank Avella
发明人： George A. Watson , Ramon S. Co , James L. Fuhrman , Frank Avella
IPC分类号： H04M9/02 , H04Q11/02 , H04J1/02
CPC分类号： H04Q11/02 , H04M9/027
摘要： A frequency multiplexed system for coupling a plurality of individual telephone sets to at least one subscriber telephone line. The system includes a line adapter unit for controlling use of subscriber lines and for assigning the use of frequency bands to the individual telephone sets. The system includes a two-conductor interconnection cable for coupling to each of the telephone sets and to the line adapter unit. The system has a power-down mode in which the loss of external power allows each of the individual telephone sets to use the subscriber line. The line adapter unit and each of the individual telephone sets employ transconductance amplifiers so that modulated current signals are produced on the interconnection cable, thus allowing a plurality of voice signals to be summed together by voltage addition for conferencing between the telephone sets and the subscriber lines. One embodiment of the invention includes the production of a pilot reference signal on the interconnection cable by the adapter unit so that synchronous modulation and demodulation by each of the telephone sets is made possible.
摘要翻译：一种用于将多个单独的电话机耦合到至少一个用户电话线路的频率复用系统。该系统包括用于控制用户线路的使用并且将频带的使用分配给各个电话机的线路适配器单元。该系统包括用于耦合到每个电话机和线路适配器单元的双导体互连电缆。该系统具有掉电模式，其中外部功率的损失允许每个单独的电话机使用用户线路。线路适配器单元和每个单独的电话机采用跨导放大器，使得在互连电缆上产生调制的电流信号，从而允许多个语音信号通过电话添加相加在电话机和用户线之间进行会议。本发明的一个实施例包括通过适配器单元在互连电缆上产生导频参考信号，使得每个电话机的同步调制和解调成为可能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式