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71. 发明授权

US07991572B2 Delay lock loop delay adjusting method and apparatus 有权
标题翻译：延迟锁环延迟调整方法及装置
公开(公告)号：US07991572B2
公开(公告)日：2011-08-02
申请号：US12730795
申请日：2010-03-24
申请人： Adrian E. Ong , Douglas W. Gorgen
发明人： Adrian E. Ong , Douglas W. Gorgen
IPC分类号： G06F19/00
CPC分类号： H03L7/0814 , H03L7/0818
摘要： Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.
摘要翻译：用于同步设备之间通信的系统和方法包括使用测试电路来测量通过延迟电路的传播时间。传播时间用于确定延迟锁定循环内的初始延迟值。然后改变该延迟值，直到找到导致同步的优选延迟值。在各种实施例中，使用初始延迟值增加了同步的速度，可靠性或其它有益特征。

72. 发明授权

US07945824B2 Processor-memory unit for use in system-in-package and system-in-module devices 有权
标题翻译：处理器内存单元，用于系统级封装和系统级模块设备
公开(公告)号：US07945824B2
公开(公告)日：2011-05-17
申请号：US12646540
申请日：2009-12-23
申请人： Adrian E. Ong , Naresh Baliga
发明人： Adrian E. Ong , Naresh Baliga
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/5602
摘要： An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
摘要翻译：一种用于在系统级封装（SiP）和系统级封装（SiP））集成电路器件中使用的处理器存储器单元的装置和方法。该装置包括处理模块，存储模块和可编程系统模块。可编程系统模块被配置为用作存储器模块和处理模块之间的接口，或者作为存储器模块和测试设备之间的接口。本发明便于包括具有不同通信协议的功能组件的处理器存储器单元的集成和测试。

73. 发明授权

US07768847B2 Programmable memory repair scheme 有权
标题翻译：可编程内存修复方案
公开(公告)号：US07768847B2
公开(公告)日：2010-08-03
申请号：US12082136
申请日：2008-04-09
申请人： Adrian E. Ong , Fan Ho
发明人： Adrian E. Ong , Fan Ho
IPC分类号： G11C7/00
CPC分类号： G11C29/76 , G11C11/401 , G11C11/4085 , G11C29/027 , G11C29/04 , G11C29/12 , G11C29/4401 , G11C29/48 , G11C29/78 , G11C29/789 , G11C29/802 , G11C2229/743
摘要： The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.
摘要翻译：本公开提供了用于测试和操作该半导体器件的方法，系统和装置。半导体存储器件包括数据存储元件和修复电路。数据存储元件包括主数据存储元件和一个或多个冗余数据存储元件，主数据存储元件具有用于存储器存取操作的相应地址。修复电路由与存储器件分开的另一个半导体器件可编程，以识别主数据存储元件的故障地址，并且编程的修复电路被配置为将存储器访问从具有识别的故障地址的主数据存储元件重新路由到相应的冗余数据存储元件。

74. 发明申请

US20100100661A1 PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES 有权
标题翻译：用于系统级封装和系统模块内设备的处理器存储单元
公开(公告)号：US20100100661A1
公开(公告)日：2010-04-22
申请号：US12646540
申请日：2009-12-23
申请人： Adrian E. Ong , Naresh Baliga
发明人： Adrian E. Ong , Naresh Baliga
IPC分类号： G06F12/06
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/5602
摘要： An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
摘要翻译：一种用于在系统级封装（SiP）和系统级封装（SiP））集成电路器件中使用的处理器存储器单元的装置和方法。该装置包括处理模块，存储模块和可编程系统模块。可编程系统模块被配置为用作存储器模块和处理模块之间的接口，或者作为存储器模块和测试设备之间的接口。本发明便于包括具有不同通信协议的功能组件的处理器存储器单元的集成和测试。

75. 发明授权

US07593271B2 Memory device including multiplexed inputs 失效
标题翻译：存储器件包括复用输入
公开(公告)号：US07593271B2
公开(公告)日：2009-09-22
申请号：US11744815
申请日：2007-05-04
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C7/10
CPC分类号： G11C5/066 , G11C8/06
摘要： Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be received at a shared conductor accessible by devices exterior to the semiconductor package and communicated to two contacts on the integrated circuit that are inaccessible to the exterior of the semiconductor package. In various embodiments, signals required to support a full set of features of the JEDEC JESD79E standard or the JEDEC JESD79-2C standard are communicated using a reduced number of exterior contacts.
摘要翻译：描述了用于减少半导体封装上的外部触点数量的系统和方法，而不减少集成电路内部对半导体封装使用的地址，数据和控制信号的数量。在一些实施例中，可以在共享导体处接收两个信号，所述共享导体可由半导体封装外部的器件访问，并且传送到集成电路上对半导体封装的外部不可访问的两个触点。在各种实施例中，使用减少数量的外部触点来传送支持JEDEC JESD79E标准或JEDEC JESD79-2C标准的全部特征所需的信号。

76. 发明授权

US07444575B2 Architecture and method for testing of an integrated circuit device 有权
标题翻译：集成电路设备测试的架构和方法
公开(公告)号：US07444575B2
公开(公告)日：2008-10-28
申请号：US11207518
申请日：2005-08-19
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31926 , G01R31/31723 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G01R31/31917
摘要： In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.
摘要翻译：在一个实施例中，本发明提供了一种硬件和/或软件平台，其能够对封装内的多个集成电路（IC）器件进行完全访问和可靠测试。该平台可以包括测试部件（例如，测试电路，测试焊盘，共享焊盘等），一个或多个探针卡和相关硬件，晶片探针程序，负载板和外部测试设备的相关硬件以及软件和例程用于最终测试程序。

77. 发明授权

US07443188B2 Electronic device having an interface supported testing mode 有权
标题翻译：具有接口支持测试模式的电子设备
公开(公告)号：US07443188B2
公开(公告)日：2008-10-28
申请号：US11981854
申请日：2007-10-31
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/318513 , G01R31/31701 , G01R31/3172 , G01R31/31723 , G01R31/319 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H01L2224/05554 , H01L2224/48139
摘要： A system is provided for testing a logic device and an integrated circuit disposed within a semiconductor device package. The logic device may be configured to operate in at least a normal mode and a test mode. A terminal external to the semiconductor device package may be electronically coupled to the logic device and the integrated circuit. The terminal may be configured to operate as a shared input for the logic device and the integrated circuit. A multiplexer circuit may be configured to convey a first signal from the terminal to the logic device in the test mode, to convey a second signal from the integrated circuit to the logic device in the normal mode, and to receive a third signal from the integrated circuit for causing a transition between the normal mode and the test mode.
摘要翻译：提供一种用于测试逻辑器件和设置在半导体器件封装内的集成电路的系统。逻辑器件可以被配置为至少在正常模式和测试模式下操作。半导体器件封装外部的端子可以电连接到逻辑器件和集成电路。终端可以被配置为作为用于逻辑设备和集成电路的共享输入。多路复用器电路可以被配置为在测试模式中将来自终端的第一信号传送到逻辑设备，以在正常模式下将第二信号从集成电路传送到逻辑器件，并且从集成导致正常模式和测试模式之间转换的电路。

78. 发明授权

US07313740B2 Internally generating patterns for testing in an integrated circuit device 有权
标题翻译：内部生成集成电路设备中的测试模式
公开(公告)号：US07313740B2
公开(公告)日：2007-12-25
申请号：US11083473
申请日：2005-03-18
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G01R31/31813 , G11C2029/3602 , H01L24/06 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49109 , H01L2224/49175 , H01L2924/01021 , H01L2924/01055 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： In a first integrated circuit chip contained in a single package along with a second integrated circuit chip, a system includes circuitry on the first integrated circuit chip for receiving address signals from the second integrated circuit chip during normal operation. Circuitry on the first integrated circuit chip generates address signals for use in testing the first integrated chip in a test mode.
摘要翻译：在与第二集成电路芯片一起包含在单个封装中的第一集成电路芯片中，系统包括第一集成电路芯片上的电路，用于在正常操作期间从第二集成电路芯片接收地址信号。第一集成电路芯片上的电路产生用于在测试模式下测试第一集成芯片的地址信号。

79. 发明授权

US07310000B2 Integrated circuit testing module including command driver 有权
标题翻译：集成电路测试模块包括命令驱动程序
公开(公告)号：US07310000B2
公开(公告)日：2007-12-18
申请号：US11443872
申请日：2006-05-30
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/31922 , G11C29/1201 , G11C29/48 , G11C29/56 , G11C29/56004 , G11C29/56012 , G11C2029/5602 , G11C2029/5606 , G11C2207/104
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
摘要翻译：公开了测试集成电路的系统和方法。该系统包括被配置为在自动测试设备和要测试的集成电路之间操作的测试模块。测试接口被配置为以比自动化测试设备配置为运行的更高的时钟频率测试集成电路。为了这样做，测试接口包括被配置用于生成要提供给集成电路的地址和测试数据的组件。可以生成各种测试数据模式，并且测试数据可以取决于地址。

80. 发明申请

US20070263458A1 Memory Device Including Multiplexed Inputs 失效
标题翻译：包含复用输入的存储器
公开(公告)号：US20070263458A1
公开(公告)日：2007-11-15
申请号：US11744815
申请日：2007-05-04
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C7/10
CPC分类号： G11C5/066 , G11C8/06
摘要： Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be received at a shared conductor accessible by devices exterior to the semiconductor package and communicated to two contacts on the integrated circuit that are inaccessible to the exterior of the semiconductor package. In various embodiments, signals required to support a full set of features of the JEDEC JESD79E standard or the JEDEC JESD79-2C standard are communicated using a reduced number of exterior contacts.
摘要翻译：描述了用于减少半导体封装上的外部触点数量的系统和方法，而不减少集成电路内部对半导体封装使用的地址，数据和控制信号的数量。在一些实施例中，可以在共享导体处接收两个信号，该共享导体可由半导体封装外部的器件访问，并且传送到集成电路上对半导体封装的外部不可访问的两个触点。在各种实施例中，使用减少数量的外部触点来传送支持JEDEC JESD79E标准或JEDEC JESD79-2C标准的全部特征所需的信号。

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