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71. 发明申请

US20080172548A1 Method and apparatus for measuring performance during speculative execution 有权
标题翻译：用于在推测执行期间测量性能的方法和装置
公开(公告)号：US20080172548A1
公开(公告)日：2008-07-17
申请号：US11654270
申请日：2007-01-16
申请人： Paul Caprioli , Shailender Chaudhry , Sherman H. Yip
发明人： Paul Caprioli , Shailender Chaudhry , Sherman H. Yip
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F9/3863 , G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F11/348 , G06F2201/88 , G06F2201/885
摘要： One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.
摘要翻译：本发明的一个实施例提供了一种用于在推测执行期间测量处理器性能的系统。系统通过在正常执行模式下执行指令来启动。然后，系统进入推测执行情节，其中指令被推测地执行而不致力于处理器的架构状态。在进入推测执行情节时，系统启用推测执行监视器。然后，系统使用推测执行监视器在推测执行情节期间监视指令，以记录与推测执行情节相关的数据值。返回到正常执行模式后，系统将禁用推测执行监视器。由推测执行监视器记录的数据值有助于在推测执行期间测量处理器的性能。

72. 发明申请

US20080126883A1 Method and apparatus for reporting failure conditions during transactional execution 有权
标题翻译：在事务执行期间报告故障条件的方法和装置
公开(公告)号：US20080126883A1
公开(公告)日：2008-05-29
申请号：US11495452
申请日：2006-07-27
申请人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
发明人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
IPC分类号： G06F11/14
CPC分类号： G06F11/1407 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3857 , G06F9/467 , G06F11/0724 , G06F11/079
摘要： One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.
摘要翻译：本发明的一个实施例提供一种在事务执行期间报告故障原因的系统。在操作期间，系统在程序中事务地执行指令块。如果指令块的事务执行成功完成，则系统将在事务执行期间进行更改，并通过指令块恢复程序的正常非事务性执行。否则，如果指令块的事务执行失败，则系统将丢弃在事务执行期间所做的更改，并记录指示事务执行失败的原因的故障信息。

73. 发明授权

US07277989B2 Selectively performing fetches for store operations during speculative execution 有权
标题翻译：在投机执行期间选择性地执行存储操作的提取
公开(公告)号：US07277989B2
公开(公告)日：2007-10-02
申请号：US11083264
申请日：2005-03-16
申请人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
发明人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
IPC分类号： G06F12/00
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3834 , G06F12/0862
摘要： One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.
摘要翻译：本发明的一个实施例提供一种处理器，其在推测执行期间选择性地取出用于存储指令的高速缓存行。在正常执行期间，处理器以程序顺序发出执行指令。当遇到产生发射条件的指令时，处理器执行检查点并以推测执行模式开始执行指令。在推测执行模式期间遇到存储指令时，处理器检查L1数据高速缓存以获得匹配的高速缓存线，并将商店的存储缓冲区检查到匹配的高速缓存行。如果在L1数据高速缓存中已经存在匹配的高速缓存行，或者如果存储到存储缓冲器中的存储到匹配的高速缓存行，则处理器抑制对高速缓存行的提取的生成。否则，处理器生成缓存行的提取。

74. 发明授权

US07216219B2 Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor 有权
标题翻译：用于在执行前处理器中避免读取后读数危险的方法和装置
公开(公告)号：US07216219B2
公开(公告)日：2007-05-08
申请号：US10923218
申请日：2004-08-20
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/30
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： One embodiment of the present invention provides a system that avoids write-after-read (WAR) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. While deferring the instruction, the system stores the instruction along with any resolved source operands for the instruction into a deferred buffer.
摘要翻译：本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免读后读取（WAR）危险的系统。系统以正常执行模式启动，其中系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，系统产生检查点，延迟指令并执行执行模式中的后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他非递延指令按程序顺序执行。在延迟指令的同时，系统将指令与指令的任何解析的源操作数一起存储到延迟缓冲区中。

75. 发明申请

US20070050601A1 Avoiding live-lock in a processor that supports speculative execution 有权
标题翻译：避免在支持推测性执行的处理器中实时锁定
公开(公告)号：US20070050601A1
公开(公告)日：2007-03-01
申请号：US11210557
申请日：2005-08-23
申请人： Shailender Chaudhry , Paul Caprioli , Sherman Yip , Guarav Garg , Ketaki Rao
发明人： Shailender Chaudhry , Paul Caprioli , Sherman Yip , Guarav Garg , Ketaki Rao
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3863 , G06F9/3885
摘要： One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode. Using the forward progress buffer in this way prevents the processor from entering a potential live-lock state.
摘要翻译：本发明的一个实施例提供一种避免在支持推测执行的处理器中的实时锁定状态的系统。系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。在执行使处理器进入推测执行模式的指令（“启动指令”）期间遇到启动条件时，系统检查与前进进程缓冲器相关联的状态指示符。如果状态指示灯指示前进进度缓冲区包含启动指令的数据，系统将恢复正常执行模式。在恢复正常执行模式时，系统从包含在前进进程缓冲器中的数据字段检索数据，并使用检索到的数据作为启动指令的输入数据执行启动指令。系统接下来取消状态指示。然后，系统在正常执行模式下继续发出以程序顺序执行的指令。以这种方式使用前进进程缓冲区可以防止处理器进入潜在的实时锁定状态。

76. 发明申请

US20060212688A1 Generation of multiple checkpoints in a processor that supports speculative execution 有权
标题翻译：在支持推测性执行的处理器中生成多个检查点
公开(公告)号：US20060212688A1
公开(公告)日：2006-09-21
申请号：US11084655
申请日：2005-03-18
申请人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
发明人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
IPC分类号： G06F9/44
CPC分类号： G06F9/3863 , G06F9/383 , G06F9/3842
摘要： One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute-ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint. Returning to the additional checkpoint prevents the processor from having to re-execute instructions between the previous checkpoint and the additional checkpoint.
摘要翻译：本发明的一个实施例提供一种在支持推测执行的处理器中创建多个检查点的系统。系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。在使处理器进入执行模式的指令期间遇到启动条件时，系统执行初始检查点并以执行提前模式开始执行指令。在执行提前模式期间遇到预定义的条件时，系统生成附加检查点，并以执行提前模式继续执行指令。如果处理器随后遇到需要处理器返回到检查点的条件，则生成附加检查点将允许处理器返回到附加检查点，而不是先前检查点。返回到附加检查点可防止处理器重新执行上一个检查点和附加检查点之间的指令。

77. 发明申请

US20050278509A1 Mechanism for eliminating the restart penalty when reissuing deferred instructions 有权
标题翻译：重新发布延期指示时消除重启罚款的机制
公开(公告)号：US20050278509A1
公开(公告)日：2005-12-15
申请号：US11058521
申请日：2005-02-14
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3863
摘要： One embodiment of the present invention provides a system which facilitates eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is resolved during execute-ahead mode, the processor begins to execute the deferred instructions in a deferred mode. In doing so, the processor initially issues deferred instructions, which have already been decoded, from a deferred queue. Simultaneously, the processor feeds instructions from a deferred SRAM into the decode unit, and these instructions eventually pass into the deferred queue. In this way, at the start of deferred mode, deferred instructions can issue from the deferred queue without having to pass through the decode unit, thereby providing time for deferred instructions from the deferred SRAM to pass through the decode unit.
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器中重新发布延迟指令时有助于消除重新启动损失的系统。在正常执行模式下，系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他非延迟指令以程序顺序执行。当在执行提前模式下解决未解决的数据依赖关系时，处理器开始以延迟模式执行延迟指令。在这样做时，处理器最初从延迟队列中发出已被解码的延迟指令。同时，处理器将来自延迟SRAM的指令送入解码单元，并且这些指令最终进入延迟队列。以这种方式，在延迟模式开始时，延迟指令可以从延迟队列发出，而不必通过解码单元，从而为延迟的SRAM提供延迟指令的时间以通过解码单元。

78. 发明申请

US20050268075A1 Multiple branch predictions 有权
标题翻译：多个分支预测
公开(公告)号：US20050268075A1
公开(公告)日：2005-12-01
申请号：US11068626
申请日：2005-02-28
申请人： Paul Caprioli , Shailender Chaudhry
发明人： Paul Caprioli , Shailender Chaudhry
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/3848
摘要： Concurrently branch predicting for multiple branch-type instructions demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the instruction flow for a high bandwidth pipeline utilized in advanced performance environments. Branch predictions are concurrently generated for multiple branch-type instructions. The concurrently generated branch predictions are then supplied for further processing of the corresponding branch-type instructions.
摘要翻译：同时分支预测多种分支式指令对高性能环境的要求。多分支式指令的并行预测为高级性能环境中使用的高带宽管道提供了指令流程。对于多个分支类型的指令同时生成分支预测。然后提供同时产生的分支预测用于进一步处理对应的分支型指令。

79. 发明申请

US20050251665A1 Method and apparatus for avoiding WAR hazards in an execute-ahead processor 有权
标题翻译：用于在执行前处理器中避免WAR危险的方法和装置
公开(公告)号：US20050251665A1
公开(公告)日：2005-11-10
申请号：US10923218
申请日：2004-08-20
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： One embodiment of the present invention provides a system that avoids write-after-read (WAR) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. While deferring the instruction, the system stores the instruction along with any resolved source operands for the instruction into a deferred buffer.
摘要翻译：本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免读后读取（WAR）危险的系统。系统以正常执行模式启动，其中系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，系统产生检查点，延迟指令并执行执行模式中的后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他非递延指令按程序顺序执行。在延迟指令的同时，系统将指令与指令的任何解析的源操作数一起存储到延迟缓冲区中。

80. 发明授权

US11048516B2 Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array 有权
公开(公告)号：US11048516B2
公开(公告)日：2021-06-29
申请号：US14752891
申请日：2015-06-27
申请人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
发明人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
IPC分类号： G06F9/38 , G06F9/30
摘要： Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.

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