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71. 发明授权

US07899943B2 PCI express enhancements and extensions 有权
公开(公告)号：US07899943B2
公开(公告)日：2011-03-01
申请号：US11933126
申请日：2007-10-31
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Arraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Arraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00 , G06F13/14
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

72. 发明申请

US20100278195A1 Packetized Interface For Coupling Agents 有权
标题翻译：耦合代理的分组接口
公开(公告)号：US20100278195A1
公开(公告)日：2010-11-04
申请号：US12431988
申请日：2009-04-29
申请人： Mahesh Wagh , Abhishek Singhal , Jasmin Ajanovic
发明人： Mahesh Wagh , Abhishek Singhal , Jasmin Ajanovic
IPC分类号： H04L29/04
CPC分类号： H04L69/22 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括在第一半导体管芯上的结构，以根据片上协议与管芯上的至少一个代理进行通信，以及耦合到该结构的分组层，以从该结构接收命令和数据信息多个链路并且将信息分组成分组，以经由内部分组化链路从芯片传输到另一个管芯。描述和要求保护其他实施例。

73. 发明申请

US20080196034A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
标题翻译： PCI EXPRESS增强和扩展
公开(公告)号：US20080196034A1
公开(公告)日：2008-08-14
申请号：US11933143
申请日：2007-10-31
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanaliur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Arraham) Mendelson , Ilan Pardo , Eran Tamari , Ellezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanaliur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Arraham) Mendelson , Ilan Pardo , Eran Tamari , Ellezer Weissmann , Doron Shamia
IPC分类号： G06F9/46
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

74. 发明授权

US07210000B2 Transmitting peer-to-peer transactions through a coherent interface 有权
标题翻译：通过一致的界面传输对等交易
公开(公告)号：US07210000B2
公开(公告)日：2007-04-24
申请号：US10832607
申请日：2004-04-27
申请人： Kenneth C. Creta , Robert G. Blankenship , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth C. Creta , Robert G. Blankenship , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F13/00 , H03M13/00
CPC分类号： G06F13/387 , G06F13/4265
摘要： In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.
摘要翻译：在各种实施例中，本发明包括一种用于在相干系统的第一代理处从第一对等设备接收具有第一报头信息的交易的方法，将第二报头信息插入事务，并且使用第二标题信息。在一个这样的实施例中，第一报头可以是第一协议的报头，并且第二报头可以是用于通过相干系统隧道交易的不同协议。

75. 发明申请

US20050251611A1 Transmitting peer-to-peer transactions through a coherent interface 有权
标题翻译：通过一致的界面传输对等交易
公开(公告)号：US20050251611A1
公开(公告)日：2005-11-10
申请号：US10832607
申请日：2004-04-27
申请人： Kenneth Creta , Robert Blankenship , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth Creta , Robert Blankenship , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F13/36 , G06F13/38 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4265
摘要： In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.
摘要翻译：在各种实施例中，本发明包括一种用于在相干系统的第一代理处从第一对等设备接收具有第一报头信息的交易的方法，将第二报头信息插入事务，并且使用第二标题信息。在一个这样的实施例中，第一报头可以是第一协议的报头，并且第二报头可以是用于通过相干系统隧道交易的不同协议。

76. 发明申请

US20050235067A1 Write combining protocol between processors and chipsets 失效
标题翻译：在处理器和芯片组之间写入组合协议
公开(公告)号：US20050235067A1
公开(公告)日：2005-10-20
申请号：US10828872
申请日：2004-04-20
申请人： Kenneth Creta , Aaron Spink , Lance Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth Creta , Aaron Spink , Lance Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F13/14 , G06F13/40
CPC分类号： G06F13/4027
摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
摘要翻译：处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

77. 发明授权

US06636912B2 Method and apparatus for mode selection in a computer system 有权
标题翻译：计算机系统中模式选择的方法和装置
公开(公告)号：US06636912B2
公开(公告)日：2003-10-21
申请号：US09414974
申请日：1999-10-07
申请人： Jasmin Ajanovic , David J. Harriman , David I. Poisner
发明人： Jasmin Ajanovic , David J. Harriman , David I. Poisner
IPC分类号： G06F1310
CPC分类号： H04L12/12 , Y02D50/40
摘要： According to one embodiment, a computer comprises a central processing unit (CPU), a first hub agent, a first hub interface coupled to the first hub agent, and a second hub agent coupled to the first hub interface. The first and second hub agents operate at a first data clocking rate determined by exchanging data clocking rate capabilities.
摘要翻译：根据一个实施例，计算机包括中央处理单元（CPU），第一集线器代理，耦合到第一集线器代理的第一集线器接口以及耦合到第一集线器接口的第二集线器代理。第一和第二中枢代理以通过交换数据时钟速率能力确定的第一数据时钟速率操作。

78. 发明授权

US06615306B1 Method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface 有权
标题翻译：用于减少流量控制并最小化集线器接口中的接口采集延迟的方法和装置
公开(公告)号：US06615306B1
公开(公告)日：2003-09-02
申请号：US09433913
申请日：1999-11-03
申请人： Jasmin Ajanovic
发明人： Jasmin Ajanovic
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： A method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface is a method of transferring data between a control hub coupled to a hub interface which is coupled to an input-output hub including the following: Transferring the data in packets. Prioritizing isochronous transfers over asynchronous transfers. Limiting asynchronous transfers to 32 bytes per packet when an agent requests the hub interface, and limiting asynchronous transfers to 64 bytes per packet when no requests for the hub interface are recognized.
摘要翻译：用于减少流量控制并最小化集线器接口中的接口捕获延迟的方法和装置是在耦合到集线器接口的控制集线器之间传送数据的方法，该集线器接口耦合到包括以下的输入 - 输出集线器：传送数据包。通过异步传输优先等时传输。当代理请求集线器接口时，将异步传输限制为每个数据包32个字节，并且当不识别到集线器接口的请求时，将异步传输限制为每个数据包64字节。

79. 发明授权

US06199127B1 Method and apparatus for throttling high priority memory accesses 失效
标题翻译：用于节流高优先级存储器访问的方法和装置
公开(公告)号：US06199127B1
公开(公告)日：2001-03-06
申请号：US08998407
申请日：1997-12-24
申请人： Jasmin Ajanovic
发明人： Jasmin Ajanovic
IPC分类号： G06F1300
CPC分类号： G06F13/18 , G06F13/1605
摘要： A method and apparatus for throttling high priority memory accesses. An apparatus of the present invention includes an arbiter circuit and a throttling circuit. The arbiter circuit is coupled to receive first and second types of memory access commands and has a preference for the first type of memory access commands. The throttling circuit is coupled to the arbiter and can at least temporarily reduce the preference for the memory access commands of the first type.
摘要翻译：一种用于节流高优先级存储器访问的方法和装置。本发明的装置包括一个仲裁器电路和一个节流电路。仲裁器电路被耦合以接收第一和第二类型的存储器访问命令，并且优先选择第一类型的存储器访问命令。节流电路耦合到仲裁器，并且可以至少暂时减少对第一类型的存储器访问命令的偏好。

80. 发明授权

US5978952A Time-distributed ECC scrubbing to correct memory errors 失效
标题翻译：时间分配的ECC擦除来纠正内存错误
公开(公告)号：US5978952A
公开(公告)日：1999-11-02
申请号：US777252
申请日：1996-12-31
申请人： George R. Hayek , Radhakrishnan Venkataraman , Jasmin Ajanovic
发明人： George R. Hayek , Radhakrishnan Venkataraman , Jasmin Ajanovic
IPC分类号： G06F11/10 , G11C11/403 , G06F11/00 , G11C29/00
CPC分类号： G06F11/106 , G11C29/52 , G06F11/1028 , G06F11/1052 , G11C2029/0409
摘要： Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section--the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors. System management interrupts and firmware may be used to implement the memory-error scrub routine, which makes it independent of and transparent to the various operating systems that may be run on the computer system.
摘要翻译：误差校正电路尝试检测并校正计算机系统内随机存取存储器（RAM）内的错误字。 RAM错误被擦除或校正回内存，而不会延迟内存访问周期。相反，包含可纠正错误的部分或一行RAM的地址被锁存，供以后由中断驱动的固件内存错误擦除例程使用。该例程读取并重写所指示的存储器部分中的每个单词 - 读取该错误的单词，在读取时在其上进行正确校正，然后将其重写回存储器。如果存储器部分的大小超过预定阈值，则将该部分的读取和重写的处理分成使用延迟的中断机制在时间上分布的更小的子进程。每个内存清理子进程的持续时间保持足够短，以免在擦除RAM内存错误的内务任务时计算机系统的响应时间不会受损。可以使用系统管理中断和固件来实现内存错误擦除例程，这使其独立于可能在计算机系统上运行的各种操作系统的透明度。

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