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71. 发明授权

US07928539B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07928539B2
公开(公告)日：2011-04-19
申请号：US12018245
申请日：2008-01-23
申请人： Yasutaka Nakashiba
发明人： Yasutaka Nakashiba
IPC分类号： H01L23/52
CPC分类号： H01L23/585 , H01L23/522 , H01L23/5227 , H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the dummy conductor patterns (20) is equivalent to a shape with an internal angle larger than 180°.
摘要翻译：半导体器件（1）包括布线（10）和虚设导体图案（20）。布线（10）是流过5GHz以上的电流的布线。在布线（10）附近，形成虚设导体图案（20）。每个虚设导体图案（20）的平面形状等同于内角大于180°的形状。

72. 发明申请

US20090302420A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090302420A1
公开(公告)日：2009-12-10
申请号：US12453736
申请日：2009-05-20
申请人： Yasutaka Nakashiba
发明人： Yasutaka Nakashiba
IPC分类号： H01L29/86
CPC分类号： H01L27/0617 , H01L23/5227 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring layer 400, a first inductor 310 and a second inductor 320 are formed on a substrate 10. The multilayer wiring layer is formed by alternately stacking an insulating layer and a wiring layer in this order t or more times (t≧3). The first inductor 310 is provided in the nth wiring layer in the multilayer wiring layer 400. The second inductor 320 is provided in the mth wiring layer in the multilayer wiring layer 400 (t≧m≧n+2) and positioned above the first inductor 310. No inductor is provided in any of the wiring layers positioned between the nth wiring layer and the mth wiring layer to be positioned above the first inductor 310. The first inductor 310 and the second inductor 320 constitute a signal transmitting device 300 which transmits an electrical signal in either of two directions.
摘要翻译：多层布线层400，第一电感器310和第二电感器320形成在基板10上。多层布线层通过以下次序交替堆叠绝缘层和布线层来形成（t> = 3 ）。第一电感器310设置在多层布线层400中的第n布线层中。第二电感器320设置在多层布线层400中的第m布线层（t> = m> = n + 2）中并且位于第一电感器310.位于第n布线层和第m布线层之间的布线层中的任何布线层中都不设置电感器以位于第一电感器310的上方。第一电感器310和第二电感器320构成信号发送装置300，在两个方向中的任一方向发送电信号。

73. 发明授权

US07211875B2 Voltage-controlled capacitive element and semiconductor integrated circuit 有权
标题翻译：压控电容元件和半导体集成电路
公开(公告)号：US07211875B2
公开(公告)日：2007-05-01
申请号：US10819123
申请日：2004-04-07
申请人： Susumu Kurosawa , Yuki Fujimoto , Yasutaka Nakashiba
发明人： Susumu Kurosawa , Yuki Fujimoto , Yasutaka Nakashiba
IPC分类号： H01L29/66
CPC分类号： H01L29/94
摘要： An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+ diffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the p+ diffusion regions are connected to a ground potential wiring. Further, an n+ diffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two p+ diffusion regions absorb positive holes serving as minority carriers from a channel region.
摘要翻译：在P型基板的上表面设置有N阱，栅极绝缘膜和栅电极配置在其上，栅电极与栅极端子连接。两个p + +扩散区被放置在夹入栅电极的N阱表面的两个区域中，并且p + +扩散区连接到地电位布线。此外，n阱扩散区域设置在N阱的表面中，并且连接到阱端子。因此，在变容二极管元件的栅电极和N阱之间产生电容。当栅极端子的电位降低时，两个p + SUP扩散区域从沟道区域吸收用作少数载流子的正空穴。

74. 发明申请

US20070013028A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070013028A1
公开(公告)日：2007-01-18
申请号：US11483533
申请日：2006-07-11
申请人： Takuji Onuma , Yasutaka Nakashiba
发明人： Takuji Onuma , Yasutaka Nakashiba
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76807 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L28/40 , H01L2924/0002 , Y10S257/924 , Y10S438/957 , H01L2924/00
摘要： A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via plug). In the semiconductor device 1, the conductive layer 14, the insulating layer 20 and the conductive layer 30 constitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer 14, the insulating layer 20 and the conductive layer 30 serve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layer 40 covers both the conductive layer 30 and the interconnect 12. The insulating layer 40 works as the etching stopper for the via plugs 52, 54.
摘要翻译：半导体器件1包括布线12，导电层14（第一导电层），绝缘层20（第一绝缘层），另一导电层30（第二导电层），另一绝缘层40（第二绝缘层），通过插头52（第一通孔插头）和另一个通孔插头54（第二通孔插头）。在半导体器件1中，导电层14，绝缘层20和导电层30构成MIM电容器（电容元件）。更详细地说，导电层14，绝缘层20和导电层30分别用作下电极，绝缘电容器膜和上电极。绝缘层40覆盖导电层30和互连12。绝缘层40用作通孔塞52,54的蚀刻阻挡件。

75. 发明申请

US20060208816A1 Piezo-oscillator 有权
标题翻译：压电振荡器
公开(公告)号：US20060208816A1
公开(公告)日：2006-09-21
申请号：US10566287
申请日：2004-08-03
申请人： Tsuyoshi Ohshima , Shigehisa Kurogo , Masayuki Ishikawa , Susumu Kurosawa , Yuki Fujimoto , Yasutaka Nakashiba
发明人： Tsuyoshi Ohshima , Shigehisa Kurogo , Masayuki Ishikawa , Susumu Kurosawa , Yuki Fujimoto , Yasutaka Nakashiba
IPC分类号： H03B5/32
CPC分类号： H01L27/0811 , H01L27/0808 , H03B5/04 , H03B5/366
摘要： Deterioration in frequency stability with time in a conventional piezoelectric oscillator using an accumulation type MOS capacitance element is improved. A P-channel transistor type or an N-channel transistor type is used as a MOS capacitance element in a variable capacitance circuit used in a piezoelectric oscillator. A bias voltage is applied between P-type or N-type extraction electrodes formed in source and drain regions and an N-type extraction electrode provided in an N-well region or a P-type extraction electrode provided in a P-well region. Instability in the MOS capacitance element with time is thus eliminated.
摘要翻译：在使用积聚型MOS电容元件的传统压电振荡器中频率稳定性随着时间的劣化得到改善。在压电振荡器中使用的可变电容电路中，使用P沟道晶体管或N沟道晶体管型作为MOS电容元件。在源极和漏极区域中形成的P型或N型引出电极之间施加偏压，设置在设置在P阱区域的N阱区域或P型引出电极中的N型引出电极。因此消除了具有时间的MOS电容元件的不稳定性。

76. 发明授权

US07088195B2 Voltage controlled oscillator having varactor and transistor regions underlying spiral conductors 有权
标题翻译：压控振荡器具有可变电抗器和位于螺旋导体下方的晶体管区域
公开(公告)号：US07088195B2
公开(公告)日：2006-08-08
申请号：US10863389
申请日：2004-06-09
申请人： Yoshinori Muramatsu , Yasutaka Nakashiba
发明人： Yoshinori Muramatsu , Yasutaka Nakashiba
IPC分类号： H03B5/08
CPC分类号： H03B5/1228 , H01L2924/0002 , H03B5/1215 , H03B5/124 , H01L2924/00
摘要： An LC-VCO in which two spiral inductors are provided in layers of a multilayer interconnection layer, while varactor elements and N-channel transistors are positioned in an region underlying the two spiral inductors, the region excluding the center axes of the spiral inductors. This allows use of a reduced layout area for the LC-VCO, while preventing magnetic fields created by the spiral inductors from having adverse effects on the operation of the varactor elements and the N-channel transistors.
摘要翻译： LC-VCO，其中两个螺旋电感器设置在多层互连层的层中，而变容二极管元件和N沟道晶体管位于两个螺旋电感器下面的区域中，该区域不包括螺旋电感器的中心轴。这允许使用用于LC-VCO的减少的布局面积，同时防止由螺旋电感器产生的磁场对变容二极管元件和N沟道晶体管的操作产生不利影响。

77. 发明申请

US20060170072A1 Circuit board and semiconductor device 有权
公开(公告)号：US20060170072A1
公开(公告)日：2006-08-03
申请号：US11340682
申请日：2006-01-27
申请人： Yasutaka Nakashiba
发明人： Yasutaka Nakashiba
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01F17/0013 , H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/1423 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H05K1/0233 , H05K1/111 , H05K1/165 , H05K2201/0792 , H05K2201/09809 , H05K2201/10674 , Y02P70/611 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated.

78. 发明申请

US20060022230A1 Solid-state image sensing device and method for manufacturing the same 有权
标题翻译：固体摄像装置及其制造方法
公开(公告)号：US20060022230A1
公开(公告)日：2006-02-02
申请号：US11155643
申请日：2005-06-20
申请人： Junichi Yamamoto , Yasutaka Nakashiba
发明人： Junichi Yamamoto , Yasutaka Nakashiba
IPC分类号： H01L21/00 , H01L31/062
CPC分类号： H01L27/14689 , H01L27/14634 , H01L27/14806
摘要： In the solid-state image sensing device, a first N type semiconductor region and an N well of a PMOS region are formed in the same process, thereby making the first N type semiconductor region and the N well in the PMOS region substantially equal in N type impurity concentration-depth profile. By forming the first N type semiconductor region and the N well in the same process, the number of manufacturing process for the solid-state image sensing device can be decreased. It is, therefore, possible to suppress excessive application of heat history to the solid-state image sensing device during ion implantation and diffusion of N type impurity. Accordingly, by suppressing excessive diffusion of impurity and the like resulting from the excessive application of the heat history to the solid-state image sensing device, yield of the solid-state image sensing device can be improved.
摘要翻译：在固态摄像装置中，以相同的工序形成PMOS区域的第一N型半导体区域和N阱，由此使PMOS区域中的第一N型半导体区域和N阱在N上基本相等型杂质浓度 - 深度剖面。通过在相同的工艺中形成第一N型半导体区域和N阱，可以减少固态图像感测装置的制造工艺的数量。因此，可以在N型杂质的离子注入和扩散期间抑制对固态摄像装置的过热应用。因此，通过抑制由于过度地将热历史应用于固体摄像装置而导致的杂质等的过度扩散，能够提高固体摄像装置的产量。

79. 发明申请

US20050189602A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050189602A1
公开(公告)日：2005-09-01
申请号：US11066534
申请日：2005-02-28
申请人： Ryota Yamamoto , Yasutaka Nakashiba
发明人： Ryota Yamamoto , Yasutaka Nakashiba
IPC分类号： H01L21/76 , H01L21/761 , H01L21/765 , H01L21/822 , H01L23/58 , H01L27/04 , H01L29/00 , H01L29/06 , H01L29/51 , H01L29/74 , H01L31/111
CPC分类号： H01L21/765 , H01L21/761 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p type silicon substrate is formed as a non-doped region with no impurity implanted. Then, a positive power supply potential is applied to the electrode. In this way, a depletion layer is formed directly under the electrode at the surface of the p type silicon substrate. Consequently, the substrate noise is shielded.
摘要翻译：在p型硅衬底上的电路区域周围的区域中设置绝缘膜，并且设置框状电极以围绕绝缘膜上的电路区域。在p型硅衬底的表面的正下方的区域形成为没有杂质注入的非掺杂区域。然后，向电极施加正电源电位。以这种方式，在p型硅衬底的表面下方的电极正下方形成耗尽层。因此，衬底噪声被屏蔽。

80. 发明授权

US06784015B2 Solid state image sensor and method for fabricating the same 失效
标题翻译：固态图像传感器及其制造方法
公开(公告)号：US06784015B2
公开(公告)日：2004-08-31
申请号：US10214301
申请日：2002-08-08
申请人： Keisuke Hatano , Yasutaka Nakashiba
发明人： Keisuke Hatano , Yasutaka Nakashiba
IPC分类号： H01L2100
CPC分类号： H01L27/14689 , H01L27/14806
摘要： In a solid state image sensor, tranfer electrodes are formed by selectively etch-removing a single layer of conducting electrode material at a plurality of first regions which divide the single layer of conducting electrode material in a row direction for each one pixel. A patterned mask is formed to cover the first regions and the single layer of conducting electrode material but to expose the single layer of conducting electrode material at a second region above each of the photoelectric conversion sections, and the single layer of conducting electrode material is selectively etch-removed using the patterned mask as a mask. Thereafter, a first conductivity type impurity and a second conductivity type impurity are ion-implanted using the patterned mask and the single layer of conducting electrode material as a mask, to form the photoelectric conversion section at the second region.
摘要翻译：在固态图像传感器中，通过在多个第一区域选择性地蚀刻除去单层导电电极材料形成转移电极，该多个第一区域对于每一个像素将行的每一个像素的单层导电电极材料划分。形成图案化掩模以覆盖第一区域和单层导电电极材料，但是在每个光电转换部分上方的第二区域处暴露单层导电电极材料，并且单层导电电极材料选择性地使用图案化掩模作为掩模蚀刻去除。此后，使用图案化掩模和单层导电电极材料作为掩模将第一导电类型杂质和第二导电类型杂质离子注入，以在第二区域形成光电转换部。

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