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71. 发明授权

US06191606B1 Method and apparatus for reducing standby leakage current using input vector activation 有权
标题翻译：使用输入向量激活来减少待机漏电流的方法和装置
公开(公告)号：US06191606B1
公开(公告)日：2001-02-20
申请号：US09150869
申请日：1998-09-10
申请人： Yibin Ye , Vivek K. De
发明人： Yibin Ye , Vivek K. De
IPC分类号： H03K1716
CPC分类号： H03K19/0016
摘要： A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.
摘要翻译：一种使用输入向量激活来减少电路块中待机漏电流的技术。复合电路包括多个输入和一个或多个晶体管堆叠。至少一些晶体管堆叠被耦合到至少一个输入端。电路还包括在待机模式期间将所选择的输入矢量应用于多个输入端的逻辑。基于电路块中的一个或多个晶体管堆叠的配置来选择输入向量，以关闭晶体管堆叠中的第一数量的晶体管。第一个数字在晶体管堆叠中的最大数量的晶体管的选定百分比之内，可以通过在多个输入端施加的任何矢量来关闭。

72. 发明申请

US20090321893A1 Multi-die integrated circuit device and method 有权
标题翻译：多芯片集成电路器件及方法
公开(公告)号：US20090321893A1
公开(公告)日：2009-12-31
申请号：US12215761
申请日：2008-06-30
申请人： Dinesh Somasekhar , Tanay Karnik , Jianping Xu , Yibin Ye
发明人： Dinesh Somasekhar , Tanay Karnik , Jianping Xu , Yibin Ye
IPC分类号： H01L29/40
CPC分类号： H01L25/18 , G11C5/02 , G11C5/063 , H01L23/481 , H01L23/5286 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599
摘要： In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.
摘要翻译：在一些实施例中，提供了具有与第二管芯耦合的第一管芯的集成电路。第二裸片具有穿过其设置的通硅通孔，以提供对第一裸片的功率参考。贯通硅通孔可横向重新定位，而不会妨碍第二管芯中的电路部分。

73. 发明申请

US20080082899A1 Memory cell supply voltage control based on error detection 有权
标题翻译：基于错误检测的存储单元电源电压控制
公开(公告)号：US20080082899A1
公开(公告)日：2008-04-03
申请号：US11542007
申请日：2006-09-29
申请人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments are also disclosed.
摘要翻译：对于一个所公开的实施例，一种装置包括存储器电路，其包括存储器单元，用于检测由存储器电路的存储器单元存储的数据中的错误的错误检测电路，以及用于增加存储器电路的一个或多个存储器单元的电源电压至少部分地基于检测到的错误。还公开了其他实施例。

74. 发明申请

US20060285393A1 APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY 失效
标题翻译：用于编程存储阵列的装置和方法
公开(公告)号：US20060285393A1
公开(公告)日：2006-12-21
申请号：US11158518
申请日：2005-06-21
申请人： Fabrice Paillet , Ali Keshavarzi , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De , Tanay Karnik
发明人： Fabrice Paillet , Ali Keshavarzi , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De , Tanay Karnik
IPC分类号： G11C16/04
CPC分类号： G11C17/18
摘要： A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
摘要翻译：提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有一个设备中的单个设备一次被编程。

75. 发明申请

US20060279985A1 Purge-based floating body memory 有权
标题翻译：基于清洗的浮体记忆
公开(公告)号：US20060279985A1
公开(公告)日：2006-12-14
申请号：US11151982
申请日：2005-06-14
申请人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De , Gerhard Schrom
发明人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De , Gerhard Schrom
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016
摘要： In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.
摘要翻译：通常，在一个方面，本公开描述了包括以行和列布置的多个存储单元的存储器阵列。每个存储单元包括具有能够存储电荷的浮动体的晶体管。多个字线和清除线与存储器单元的行互连。多个位线被连接到存储器单元的列。通过字线提供的驱动信号，清除线和位线可以协作以改变一个或多个存储器单元中的浮体区域的电荷。

76. 发明申请

US20060114711A1 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US20060114711A1
公开(公告)日：2006-06-01
申请号：US11001870
申请日：2004-12-01
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan Pandya , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan Pandya , Vivek De
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
摘要翻译：在一个实施例中，提供了包括一个或多个列的存储器阵列，每个列包括被分成位单元组的多个位单元，每组比特单元可控制地耦合到单独的位线。

77. 发明申请

US20060092742A1 OTP antifuse cell and cell array 有权
标题翻译： OTP反熔丝电池和电池阵列
公开(公告)号：US20060092742A1
公开(公告)日：2006-05-04
申请号：US10979605
申请日：2004-11-01
申请人： Fabrice Paillet , Ali Keshavarzi , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Fabrice Paillet , Ali Keshavarzi , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G11C17/18
CPC分类号： G11C17/146 , G11C17/16 , G11C17/18 , G11C29/027
摘要： Different embodiments of a one-time-programmable antifuse cell are provided in this disclosure. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.
摘要翻译：本公开中提供了一次性可编程反熔丝电池的不同实施例。在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。

78. 发明申请

US20060061382A1 Majority voter apparatus, systems, and methods 失效
标题翻译：多数选民设备，制度和方法
公开(公告)号：US20060061382A1
公开(公告)日：2006-03-23
申请号：US10947765
申请日：2004-09-23
申请人： Yibin Ye , James Tschanz , Muhammad Khellah , Vivek De
发明人： Yibin Ye , James Tschanz , Muhammad Khellah , Vivek De
IPC分类号： H03K19/003
CPC分类号： H03K19/23
摘要： Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.
摘要翻译：装置和系统以及方法和物品可以使用耦合到第一多个位输入和第二多个位输入的读出放大器来提供多数选举指示。

79. 发明申请

US20060054977A1 Charge storage memory cell 审中-公开
标题翻译：充电存储单元
公开(公告)号：US20060054977A1
公开(公告)日：2006-03-16
申请号：US10942019
申请日：2004-09-16
申请人： Dinesh Somasekhar , Shekhar Borkar , Vivek De , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu
发明人： Dinesh Somasekhar , Shekhar Borkar , Vivek De , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C11/404 , G11C16/0416
摘要： A memory device is provided that includes a plurality of memory cells where each memory cell includes a source region, a drain region and a floating gate. A coupling bit-line is also provided that extends over at least one column of the plurality of memory cells. The coupling bit-line may be formed on each of the floating gates of memory cells forming the column of the plurality of memory cells. The coupling bit-line may also be formed within a well of each of memory cells forming the column of the plurality of memory cells.
摘要翻译：提供一种存储器件，其包括多个存储器单元，其中每个存储器单元包括源极区域，漏极区域和浮动栅极。还提供了在多个存储单元中的至少一列延伸的耦合位线。耦合位线可以形成在形成多个存储单元的列的存储单元的每个浮置栅极上。耦合位线也可以形成在形成多个存储器单元的列的每个存储单元的阱中。

80. 发明申请

US20050226032A1 SRAM device having forward body bias control 有权
标题翻译：具有前向偏置控制的SRAM器件
公开(公告)号：US20050226032A1
公开(公告)日：2005-10-13
申请号：US10812894
申请日：2004-03-31
申请人： Stephen Tang , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz
发明人： Stephen Tang , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
摘要翻译：提供具有多个存储单元的SRAM器件。每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体，以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。功率控制单元可以控制每个PMOS晶体管的电源电压，并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。

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