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71. 发明申请

US20050050533A1 Optimizing compiler 审中-公开
标题翻译：优化编译器
公开(公告)号：US20050050533A1
公开(公告)日：2005-03-03
申请号：US10929950
申请日：2004-08-30
申请人： Akira Koseki , Hideaki Komatsu
发明人： Akira Koseki , Hideaki Komatsu
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/441
摘要： Compiler for optimizing a load instruction in a program, including: executable range detecting means for detecting executable range of load instruction in execution paths tracing back execution procedures from a target load, where the range can hold data read by the load instruction into register and transmit data to execution position of target load instruction when load instruction is executed; instruction generating means for generating a precedent load instruction, executed prior to target load instruction in executable range, within the executable range for each of the execution paths when the precedent load instruction for reading the same data from the same address as the target load instruction is absent; and instruction replacing means for deleting the target load instruction and replacing an instruction using the data read by the target load instruction with an instruction using data which are read by the precedent load instruction.
摘要翻译：用于优化程序中的加载指令的编译器，包括：可执行范围检测装置，用于检测从目标负载追溯执行过程的执行路径中的加载指令的可执行范围，其中所述范围可以将由加载指令读取的数据保存到寄存器和发送当执行加载指令时，数据到目标加载指令的执行位置; 指令产生装置，用于当用于从与目标加载指令相同的地址读取相同数据的先前加载指令时，在每个执行路径的可执行范围内生成在可执行范围内的目标加载指令之前执行的先前加载指令，缺席; 以及指令替换装置，用于使用由先前加载指令读取的数据的指令，删除目标加载指令并使用由目标加载指令读取的数据替换指令。

72. 发明授权

US06253372B1 Determining a communication schedule between processors 失效
标题翻译：确定处理器之间的通信时间表
公开(公告)号：US06253372B1
公开(公告)日：2001-06-26
申请号：US09361316
申请日：1999-07-27
申请人： Hideaki Komatsu , Takeshi Ogasawara
发明人： Hideaki Komatsu , Takeshi Ogasawara
IPC分类号： G06F945
CPC分类号： G06F15/17368
摘要： To generate an optimum communication schedule when data is transmitted or received between processors which constitute a parallel computer or a distributed multiprocessor system. Processors which each perform inter-processor communication are sorted into a plurality of groups. A communication graph is generated whose nodes correspond to the groups and edges correspond to the communications. Communication graphs are generated for distances between nodes from one through N−1. Each communication graph corresponds to a communication step of the inter-processor communication. Communication is grasped as a whole by the communication graph and the edge of the communication graph means the inter-processor communication which is performed in a certain communication step. In this way, the communication can be optimized.
摘要翻译：当在构成并行计算机或分布式多处理器系统的处理器之间发送或接收数据时，生成最佳通信调度。每个进行处理器间通信的处理器分为多个组。生成其节点对应于组和边缘对应于通信的通信图。生成从1到N-1的节点之间的距离的通信图。每个通信图对应于处理器间通信的通信步骤。通过通信图来整体地进行通信，通信图的边缘是指在某个通信步骤中执行的处理器间通信。以这种方式，可以优化通信。

73. 发明授权

US06173562B1 Exhaust recirculation type combined plant 失效
标题翻译：排气再循环型联合厂房
公开(公告)号：US06173562B1
公开(公告)日：2001-01-16
申请号：US09022441
申请日：1998-02-12
申请人： Motoaki Utamura , Shinichi Hoizumi , Yasushi Takeda , Toshihiko Sasaki , Hideaki Komatsu , Seiichi Kirikami , Takeshi Suzumura , Tetsuo Sasada , Takashi Ikeguchi , Shigehisa Sugita
发明人： Motoaki Utamura , Shinichi Hoizumi , Yasushi Takeda , Toshihiko Sasaki , Hideaki Komatsu , Seiichi Kirikami , Takeshi Suzumura , Tetsuo Sasada , Takashi Ikeguchi , Shigehisa Sugita
IPC分类号： F02C618
CPC分类号： F02C9/20 , F01K23/101 , F02C1/007 , F02C3/34 , F02C6/18 , F02C7/10 , F02C9/16 , F05D2220/72 , Y02E20/16
摘要： To improve the thermal efficiency when an exhaust heat recovery type combined cycle plant having a gas turbine and a steam turbine in combination is operated at a partial load, the gas turbine exhaust is recirculated and returned to the compressor, and the combustion temperature is prevented from being lowered at the partial load. Preferably, the temperature is maintained constant. In this way, the thermal efficiency during operation at partial load can be improved.
摘要翻译：为了在具有燃气轮机和蒸汽轮机组合的排气热回收型联合循环装置以部分负荷运转的情况下提高热效率，燃气轮机排气再循环并返回到压缩机，并且防止燃烧温度在部分负载下降低。优选地，温度保持恒定。以这种方式，可以提高在部分负荷下操作期间的热效率。

74. 发明授权

US5625832A Distributed processing control method and distributed processing system 失效
标题翻译：分布式处理控制方法和分布式处理系统
公开(公告)号：US5625832A
公开(公告)日：1997-04-29
申请号：US388534
申请日：1995-02-14
申请人： Gyo Ohsawa , Hideaki Komatsu
发明人： Gyo Ohsawa , Hideaki Komatsu
IPC分类号： G06F15/16 , G06F9/44 , G06F9/45 , G06F9/46 , G06F15/177 , G06F13/00
CPC分类号： G06F8/45
摘要： A distributed control method and distributed processing system to decrease data communication overhead and to execute a program efficiently. One of processors at which data arrives in a multiprocessing system is selected by a polling process (310 to 312). All data which arrives at the selected processor is received therefrom to fill a control table of sending and receiving data and a control table of calculation sets with marks for indicating the completion of data receipt (314 to 316). Data to be sent is sent so that the control table of sending and receiving data is marked to indicate the completion of data sending (318 to 320). If data has not yet arrived during polling, required data is sent to all processors (322). The execution of actual calculations using array processes is effected by using calculation sets such that the control table of calculation sets is marked indicating the completion of calculation. This is repeated until all calculation sets are received and there are none present indicating that the calculation not been completed thereby indicating that "the execution of calculation is completed" (324 to 328).
摘要翻译：一种分布式控制方法和分布式处理系统，用于降低数据通信开销并有效执行程序。通过轮询处理（310〜312）选择数据到达多处理系统的处理器之一。接收到所选处理器的所有数据，以填充发送和接收数据的控制表以及用于指示数据接收完成的标记的计算集合的控制表（314至316）。发送要发送的数据，使得发送和接收数据的控制表被标记以指示数据发送的完成（318至320）。如果在轮询期间尚未到达数据，则将所需数据发送到所有处理器（322）。通过使用计算集来实现使用数组处理的实际计算的执行，使得计算集合的控制表被标记指示计算的完成。重复这一操作，直到接收到所有计算集，并且没有表示计算未完成，从而指示“计算的执行完成”（324至328）。

75. 发明授权

US08438553B2 Paralleling processing method, system and program 有权
标题翻译：并行处理方法，系统和程序
公开(公告)号：US08438553B2
公开(公告)日：2013-05-07
申请号：US12629114
申请日：2009-12-02
申请人： Hideaki Komatsu , Arquimedes Martinez Canedo , Takeo Yoshizawa
发明人： Hideaki Komatsu , Arquimedes Martinez Canedo , Takeo Yoshizawa
IPC分类号： G06F9/45
CPC分类号： G06F8/30 , G06F8/456
摘要： Paralleling processing system and method. When clusters are formed based on strongly connected components, a single cluster (fat cluster) having at least a predetermined number of blocks, or an expected processing time exceeding a predetermined threshold, is formed. The fat cluster is subjected to an unrolling process to make multiple copies of the processing of the fat cluster and to assign the copies to individual processors. Processing of the fat cluster is executed by the multiple processor devices in a pipelined manner. If a fat cluster to be iteratively executed cannot be executed in the pipelined manner because a processing result of an nth iteration of the fat cluster depends on a processing result of a preceding iteration of the fat cluster an input value needed for execution of the fat cluster is generated based on a certain prediction, and the fat cluster is speculatively executed.
摘要翻译：并行处理系统及方法。当基于强连接的组件形成集群时，形成具有至少预定数量块的单个集群（胖集群）或超过预定阈值的预期处理时间。脂肪群体经历展开过程，以便对脂肪群集的处理进行多个拷贝，并将副本分配给各个处理器。脂肪簇的处理由多个处理器设备以流水线方式执行。如果要迭代执行的胖群集不能以流水线方式执行，因为胖群的第n次迭代的处理结果取决于胖群的前一迭代的处理结果，则执行胖群所需的输入值是基于某种预测生成的，并且推测性地执行脂肪群。

76. 发明授权

US08261043B2 SIMD merge-sort and duplicate removal operations for data arrays 有权
标题翻译：数据阵列的SIMD合并排序和重复删除操作
公开(公告)号：US08261043B2
公开(公告)日：2012-09-04
申请号：US12464213
申请日：2009-05-12
申请人： Hiroshi Inoue , Moriyoshi Ohara , Hideaki Komatsu
发明人： Hiroshi Inoue , Moriyoshi Ohara , Hideaki Komatsu
IPC分类号： G06F15/80 , G06F7/16
CPC分类号： G06F7/36 , G06F9/3001 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge OR operations.
摘要翻译：提供了一种通过使用SIMD指令来执行两个或更多个数据流的有效合并操作的方法和装置。数据流并行并入缓冲或移除条件分支。数据流的合并操作包括合并和和合并或运算。

77. 发明申请

US20120110294A1 METHOD OF MEMORY MANAGEMENT FOR SERVER-SIDE SCRIPTING LANGUAGE RUNTIME SYSTEM 失效
标题翻译：服务器语言语言运行系统的内存管理方法
公开(公告)号：US20120110294A1
公开(公告)日：2012-05-03
申请号：US13344687
申请日：2012-01-06
申请人： Hiroshi Inoue , Hideaki Komatsu
发明人： Hiroshi Inoue , Hideaki Komatsu
IPC分类号： G06F12/02
CPC分类号： G06F12/0253
摘要： A method of memory management includes allocating a portion of a memory as a memory heap including a plurality of segments, each segment having a segment size; performing one or more memory allocations for objects in the memory heap; creating a free list array and class-size array in a metadata section of the memory heap, the class-size array being created such that each element of the size-class array is related a particular one of the plurality of segments and the free list array being created such that each element of the free list array is related to a different size class; and initializing the heap when it is determined that the heap may be destroyed, initializing including clearing the free list array.
摘要翻译：一种存储器管理方法包括将存储器的一部分分配为包括多个段的存储堆，每个段具有段大小; 对存储器堆中的对象执行一个或多个存储器分配; 在内存堆的元数据部分中创建自由列表数组和类大小数组，创建类大小数组，使得大小类数组的每个元素与多个片段中的特定片段和自由列表相关联数组被创建，使得自由列表数组的每个元素与不同大小的类相关; 并且当确定堆可能被破坏时初始化堆，初始化包括清除空闲列表数组。

78. 发明申请

US20120101791A1 CONTROLLING SIMULATION SYSTEMS 审中-公开
标题翻译：控制仿真系统
公开(公告)号：US20120101791A1
公开(公告)日：2012-04-26
申请号：US13246052
申请日：2011-09-27
申请人： Hideaki Komatsu , Shingo Nagai , Fumitomo Ohsawa
发明人： Hideaki Komatsu , Shingo Nagai , Fumitomo Ohsawa
IPC分类号： G06G7/48
CPC分类号： G06F17/5009 , G05B17/02 , G06F17/5095
摘要： A method for controlling a simulation system includes storing first-stage and second stage tables in which a value of a predicted time until arrival of an I/O instruction and a type of the instruction are included as entries for each program counter of an instruction set simulator, and in which a value of an earliest time until an output event from a peripheral simulator is included as an entry for each type of instruction; looking up the first-stage table to obtain the type of the instruction and the value of the predicted time until arrival of the instruction, looking up the second-stage table with reference to the obtained type of the instruction to obtain the value of the earliest time until the output event from the peripheral simulator, and returning the predicted time until arrival of the instruction and the earliest time until the output event from the peripheral simulator.
摘要翻译：一种用于控制模拟系统的方法，包括存储第一级和第二级表，其中包括I / O指令的到达之前的预测时间的值和指令的类型作为指令集的每个程序计数器的条目模拟器，并且其中包括来自外围模拟器的输出事件之前的最早时间的值作为每种类型的指令的条目; 查找第一级表以获得指令的类型和直到指令到达的预测时间的值，参考获得的指令类型来查找第二级表以获得最早的值直到来自外围模拟器的输出事件为止，并返回直到指令到达为止的预测时间和最早的时间，直到来自外围模拟器的输出事件。

79. 发明授权

US08104026B2 Compiler register allocation and compilation 失效
标题翻译：编译器寄存器分配和编译
公开(公告)号：US08104026B2
公开(公告)日：2012-01-24
申请号：US11927355
申请日：2007-10-29
申请人： Akira Koseki , Hideaki Komatsu
发明人： Akira Koseki , Hideaki Komatsu
IPC分类号： G06F9/44
CPC分类号： G06F8/441
摘要： Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.
摘要翻译：将适当的寄存器分配给多个变量。编译器将源程序转换为具有以下处理器的指令：具有：同时使用的变量获取部分，其针对源程序中使用的多个变量中的每一个获得与该变量同时使用的一些其它变量; 分配序列生成部，其生成所述多个变量之间的多个分配序列，以将每个变量分配给与所述变量同时使用的一些其他变量的多个寄存器中的一个不同的寄存器; 分配优先级获取部分，其优先级获得指示分配了多个寄存器中的每个变量的哪个寄存器的分配优先级; 以及寄存器分配部分，其根据基于分配优先级选择的分配序列将变量分配给寄存器。

80. 发明申请

US20110015916A1 SIMULATION METHOD, SYSTEM AND PROGRAM 有权
标题翻译：模拟方法，系统和程序
公开(公告)号：US20110015916A1
公开(公告)日：2011-01-20
申请号：US12834081
申请日：2010-07-12
申请人： Masaki Kataoka , Hideaki Komatsu , Goh Kondoh , Fumitomo Ohsawa
发明人： Masaki Kataoka , Hideaki Komatsu , Goh Kondoh , Fumitomo Ohsawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5095
摘要： A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing.
摘要翻译：具有彼此通信的多个外围设备的模拟系统。该系统包括权重设置为通信时间的加权图。外围设备表示为节点，连接路径表示为边。在循环中的通信时间中，将最小时间设置为第一同步定时。具有可接受延迟的定时被设置为第二同步定时。由用户设定为比第一和第二定时长的定时被设定为第三同步定时。第三同步定时用于定时可用的部分，从而在尽可能长的同步定时同步外设。

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