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71. 发明授权

US07038320B1 Single damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的单镶嵌一体化方案
公开(公告)号：US07038320B1
公开(公告)日：2006-05-02
申请号：US09785445
申请日：2001-02-20
申请人： Lu You , Fei Wang , Minh Van Ngo
发明人： Lu You , Fei Wang , Minh Van Ngo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76814 , H01L21/76834
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A second etch stop layer can also be disposed between the first diffusion barrier layer and the first etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上并与第一扩散阻挡层隔开，并且介电层设置在第一蚀刻停止层上。通孔也可以有圆角。第二蚀刻停止层也可以设置在第一扩散阻挡层和第一蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

72. 发明授权

US06989563B1 Flash memory cell with UV protective layer 有权
标题翻译：具有UV保护层的闪存单元
公开(公告)号：US06989563B1
公开(公告)日：2006-01-24
申请号：US10770260
申请日：2004-02-02
申请人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
发明人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L23/53295 , H01L23/552 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷俘获电介质闪存单元上沉积和平坦化层间电介质层，并在平坦化的层间电介质层上沉积至少一个UV保护层，UV保护层包括基本上不透紫外线的材料。

73. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

74. 发明授权

US06730587B1 Titanium barrier for nickel silicidation of a gate electrode 有权
标题翻译：用于栅电极的硅化硅的钛屏障
公开(公告)号：US06730587B1
公开(公告)日：2004-05-04
申请号：US09731006
申请日：2000-12-07
申请人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
发明人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
IPC分类号： H01L213205
CPC分类号： H01L29/4941 , H01L21/28052 , H01L29/665
摘要： Nickel silicidation of a gate electrode is controlled using a titanium barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of titanium thereon and an upper polycrystalline silicon layer on the titanium layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and a titanium silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.
摘要翻译：使用钛阻挡层来控制栅电极的镍硅化。实施例包括在钛层上形成包括下多晶硅层，钛层和上多晶硅层的栅极电极结构，沉积镍层和硅化物，由此将上多晶硅层转变为硅化镍，形成防止镍与下部多晶硅层反应的硅化钛阻挡层。

75. 发明授权

US06713874B1 Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics 有权
标题翻译：在有机掺杂的石英玻璃层间电介质上具有双重自然封盖/电弧层的半导体器件
公开(公告)号：US06713874B1
公开(公告)日：2004-03-30
申请号：US09817050
申请日：2001-03-27
申请人： Dawn M. Hopper , Lu You , Minh Van Ngo
发明人： Dawn M. Hopper , Lu You , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/3171 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on the organic-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.
摘要翻译：通过在层间电介质膜上形成双重性质覆盖/ ARC层，在制造期间降低有机掺杂石英玻璃低k层间电介质的降解显着降低，并提高亚微米特征的分辨率。在有机掺杂的石英玻璃层间电介质上原位形成封盖/ ARC层。封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

76. 发明授权

US06706576B1 Laser thermal annealing of silicon nitride for increased density and etch selectivity 有权
标题翻译：氮化硅的激光热退火以提高密度和蚀刻选择性
公开(公告)号：US06706576B1
公开(公告)日：2004-03-16
申请号：US10096741
申请日：2002-03-14
申请人： Minh Van Ngo , Angela Hui
发明人： Minh Van Ngo , Angela Hui
IPC分类号： H01L2100
CPC分类号： H01L27/11521 , H01L21/3185 , H01L21/76802 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L27/115
摘要： The density of a deposited silicon nitride layer is increased by laser thermal annealing in N2, thereby increasing etch selectivity with respect to an overlying oxide and, hence, avoiding damage to underlying silicide layers and gates. Embodiments include laser thermal annealing a silicon nitride layer deposited as an etch stop layer, e.g., in fabricating EEPROMs, to increase its density by up to about 8%, thereby increasing its etch selectivity with respect to an overlying BPSG layer to about {fraction (1/12)} to about {fraction (1/14)}.
摘要翻译：沉积的氮化硅层的密度通过在N 2中的激光热退火而增加，从而相对于上覆氧化物增加了蚀刻选择性，因此避免了对下面的硅化物层和栅极的损害。实施例包括激光热退火沉积为蚀刻停止层的氮化硅层，例如在制造EEPROM中，将其密度增加高达约8％，从而将其相对于上覆的BPSG层的蚀刻选择性增加到约{部分（ 1/12至约{部分（1/14。

77. 发明授权

US06599827B1 Methods of forming capped copper interconnects with improved electromigration resistance 有权
标题翻译：形成具有改善的电迁移阻力的封盖铜互连的方法
公开(公告)号：US06599827B1
公开(公告)日：2003-07-29
申请号：US09846273
申请日：2001-05-02
申请人： Minh Van Ngo , Steven C. Avanzino , Amit P. Marathe , Hartmut Ruelke
发明人： Minh Van Ngo , Steven C. Avanzino , Amit P. Marathe , Hartmut Ruelke
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76883
摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by pumping out the deposition chamber after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma, introducing NH3 and N2 into the deposition chamber, and then ramping up the introduction of SiH4 prior to initiating deposition of a silicon nitride capping layer. Embodiments include ramping up the introduction of SiH4 in two stages prior to initiating plasma enhanced chemical vapor deposition of the silicon nitride capping layer.
摘要翻译：通过在用含氨的等离子体处理暴露的Cu或Cu合金的平坦化表面之后，通过泵出沉积室来显着改善封盖的Cu或Cu合金互连的电迁移电阻，将NH 3和N 2引入沉积室，然后斜坡在开始沉积氮化硅覆盖层之前引入SiH4。实施例包括在引发氮化硅覆盖层的等离子体增强化学气相沉积之前分两阶段引入SiH4。

78. 发明授权

US06586333B1 Integrated plasma treatment and nickel deposition and tool for performing same 有权
标题翻译：集成等离子体处理和镍沉积和用于执行相同的工具
公开(公告)号：US06586333B1
公开(公告)日：2003-07-01
申请号：US09680264
申请日：2000-10-05
申请人： Christy Mei-Chu Woo , Minh Van Ngo
发明人： Christy Mei-Chu Woo , Minh Van Ngo
IPC分类号： H01L2100
CPC分类号： H01L21/0206 , H01L21/28518 , H01L21/2855 , H01L29/665 , H01L29/7833
摘要： A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; implanting nitrogen into the sidewall spacers; forming a nickel layer; and forming nickel suicide layers disposed on the source/drain regions and the gate electrode. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The nitrogen implantation process is a plasma treating in a plasma-enhanced chemical vapor deposition chamber, and the nickel deposition is performed in a physical deposition chamber. Also, the implantation process and the formation of the nickel layer are sequentially performed without removal from a non-oxidizing atmosphere. An implantation and deposition system for performing portions of this process is also disclosed.
摘要翻译：一种制造MOSFET半导体器件的方法包括在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 在栅电极和衬底之间提供栅极氧化物; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 将氮注入到侧壁间隔物中; 形成镍层; 以及形成设置在源/漏区和栅电极上的硅化镍层。在约380-600℃的温度下快速热退火时形成硅化镍层。氮注入工艺是等离子体增强化学气相沉积室中的等离子体处理，并且镍沉积在物理沉积室。此外，在不从非氧化性气氛中除去的情况下，依次进行注入工艺和镍层的形成。还公开了用于执行该过程的部分的植入和沉积系统。

79. 发明授权

US06566252B1 Method for simultaneous deposition and sputtering of TEOS and device thereby formed 有权
标题翻译：由此形成的TEOS和装置的同时沉积和溅射的方法
公开(公告)号：US06566252B1
公开(公告)日：2003-05-20
申请号：US09689144
申请日：2000-10-11
申请人： Paul R. Besser , Minh Van Ngo
发明人： Paul R. Besser , Minh Van Ngo
IPC分类号： H01L2144
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/76801
摘要： A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.
摘要翻译：制造0.25微米半导体芯片的方法包括使用TEOS作为高密度等离子体（HDP）层间电介质（ILD）。更具体地说，在基板上建立预定的铝线图案之后，TEOS沉积并与TEOS沉积同时被蚀刻掉，从而避免了铝线中的氢脆化和随后的空隙形成，否则如果硅烷是用作HDP ILD。

80. 发明授权

US06545370B1 Composite silicon nitride sidewall spacers for reduced nickel silicide bridging 有权
标题翻译：用于还原硅化镍桥接的复合氮化硅侧壁间隔物
公开(公告)号：US06545370B1
公开(公告)日：2003-04-08
申请号：US09679375
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser
IPC分类号： H01L27088
CPC分类号： H01L29/665 , H01L29/4983 , H01L29/6656
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by employing composite silicon nitride sidewall spacers comprising an outer layer having reduced free silicon. Embodiments include forming composite silicon nitride sidewall spacers comprising an inner silicon nitride layer, having a refractive index of about 1.95 to about 2.05 and a thickness of about 450 Å to about 550 Å, on the side surfaces of the gate electrode and an outer silicon nitride layer, having a refractive index to less than about 1.95 and a thickness of about 350 Å to about 450 Å.
摘要翻译：通过使用复合氮化硅侧壁间隔物来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接，所述复合氮化硅侧壁间隔物包括具有减少的自由硅的外层。实施例包括形成复合氮化硅侧壁间隔物，其包括内部氮化硅层，折射率为约1.95至约2.05，厚度约为450至大约的厚度在栅电极和外部氮化硅层，具有小于约1.95的折射率和约350至约的厚度。

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