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71. 发明授权

US08436429B2 Stacked power semiconductor device using dual lead frame and manufacturing method 有权
标题翻译：采用双引线框架的叠层功率半导体器件及其制造方法
公开(公告)号：US08436429B2
公开(公告)日：2013-05-07
申请号：US13118445
申请日：2011-05-29
申请人： Yan Xun Xue , Yueh-Se Ho , Lei Shi , Jun Lu , Liang Zhao
发明人： Yan Xun Xue , Yueh-Se Ho , Lei Shi , Jun Lu , Liang Zhao
IPC分类号： H01L27/088
CPC分类号： H01L23/49562 , H01L23/49524 , H01L23/49575 , H01L24/48 , H01L2224/48247 , H01L2924/00014 , H01L2924/01322 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
摘要翻译：叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。安装夹在第一半导体芯片的背面连接到电极。第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

72. 发明授权

US08067822B2 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US08067822B2
公开(公告)日：2011-11-29
申请号：US12215049
申请日：2008-06-23
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L23/52 , H01L23/485 , H01L23/495
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

73. 发明授权

US07211877B1 Chip scale surface mount package for semiconductor device and process of fabricating the same 有权
标题翻译：用于半导体器件的芯片级表面贴装封装及其制造方法
公开(公告)号：US07211877B1
公开(公告)日：2007-05-01
申请号：US11082080
申请日：2005-03-15
申请人： Felix Zandman , Y. Mohammed Kasem , Yueh-Se Ho
发明人： Felix Zandman , Y. Mohammed Kasem , Yueh-Se Ho
IPC分类号： H01L23/544 , H01L21/331
CPC分类号： H01L21/6835 , H01L21/6836 , H01L23/492 , H01L23/49805 , H01L23/49816 , H01L24/11 , H01L24/24 , H01L24/27 , H01L24/81 , H01L24/82 , H01L24/97 , H01L2221/68327 , H01L2221/68377 , H01L2224/1132 , H01L2224/13099 , H01L2224/24226 , H01L2224/274 , H01L2224/76155 , H01L2224/8121 , H01L2224/81815 , H01L2224/82102 , H01L2224/83191 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2224/82 , H01L2924/00
摘要： A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.
摘要翻译：在晶片尺寸上制造在骰子的两侧形成触点的半导体封装。晶片的背面附着在金属板上。分割骰子的划痕线被锯切以露出金属板，但切口不延伸穿过金属板。可以包括多个子层的金属层形成在骰子的前侧，金属覆盖金属板的暴露部分并延伸骰子的侧边缘。金属层的分开的部分也可以覆盖骰子正面上的连接垫。使用与用于制造第一组锯切的刀片相比较窄的第二组锯切与第一组锯切重合。结果，金属层保留在连接骰子（通过金属板）的前侧和前侧的骰子的侧边缘上。由于不需要引线键合，所以产生的封装是坚固的，并且在芯片的背面和前面之间提供低电阻电连接。

74. 发明申请

US20050280133A1 Multiple device package 审中-公开
标题翻译：多器件封装
公开(公告)号：US20050280133A1
公开(公告)日：2005-12-22
申请号：US10873743
申请日：2004-06-21
申请人： Leeshawn Luo , Anup Bhalla , Sik Lui , Yueh-Se Ho , Mike Chang , Xiao Zhang
发明人： Leeshawn Luo , Anup Bhalla , Sik Lui , Yueh-Se Ho , Mike Chang , Xiao Zhang
IPC分类号： H01L21/48 , H01L23/495
CPC分类号： H01L23/49562 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/484 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/49111 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package and method of assembling a semiconductor package is disclosed. The semiconductor package includes a first device mounted on a leadframe and a second device mounted on the leadframe. The leadframe has leads extending to the exterior of the package. An anvil may be used to mount a device on the package. The anvil may include two side portions to support the leads of the package, two end portions connected to the two side portions, and a cutout region.
摘要翻译：公开了一种组装半导体封装的半导体封装和方法。半导体封装包括安装在引线框架上的第一器件和安装在引线框架上的第二器件。引线框架具有延伸到封装外部的引线。可以使用砧座将装置安装在包装上。砧座可以包括用于支撑包装的引线的两个侧部，连接到两个侧部的两个端部和切口区域。

75. 发明申请

US20050145996A1 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US20050145996A1
公开(公告)日：2005-07-07
申请号：US10972746
申请日：2004-10-25
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik Lui , Mike Chang
IPC分类号： H01L21/60 , H01L23/485 , H01L23/495 , H01L23/50 , H01L23/34
CPC分类号： H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种具有引线框架（108）的半导体集成电路封装，该引线框架（108）包括设置在管芯（100）下方的引线框焊盘（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和管芯（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。该集成电路适用于MOSFET器件，并且焊接金属区域（101a）用于源极端子（101）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

76. 发明授权

US06841852B2 Integrated circuit package for semiconductor devices with improved electric resistance and inductance 有权
标题翻译：具有改善的电阻和电感的半导体器件的集成电路封装
公开(公告)号：US06841852B2
公开(公告)日：2005-01-11
申请号：US10189333
申请日：2002-07-02
申请人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
发明人： Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
IPC分类号： H01L21/60 , H01L23/485 , H01L23/495 , H01L23/50 , H01L23/48
CPC分类号： H01L24/85 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05552 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

77. 发明授权

US5904525A Fabrication of high-density trench DMOS using sidewall spacers 失效
标题翻译：使用侧壁间隔件制造高密度沟槽DMOS
公开(公告)号：US5904525A
公开(公告)日：1999-05-18
申请号：US646593
申请日：1996-05-08
申请人： Fwu-Iuan Hshieh , Yueh-Se Ho , Bosco Lan , Jowei Dun
发明人： Fwu-Iuan Hshieh , Yueh-Se Ho , Bosco Lan , Jowei Dun
IPC分类号： H01L21/26 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/404 , H01L29/0696 , Y10S148/126
摘要： A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers. The peripheries of the diffusion-inhibiting regions covered by the remaining portions of the first and second oxide layers inhibit lateral diffusion of the deep body diffusions without significantly inhibiting diffusion depth.
摘要翻译：一种用于形成具有在半导体衬底上形成的外延层上占据最小面积的深体区的沟槽DMOS晶体管的方法。第一氧化物层形成在外延层上并且被图案化以限定将在其下形成深体区域的深体区域。接下来，在形成覆盖深体区域的第二氧化物层和第一氧化物层的剩余部分之前，在每个深体区域中形成第一导电类型的扩散抑制区域。然后去除第二氧化物层的部分以暴露扩散抑制区域的中心，从第二氧化物层留下第一氧化物层和氧化物侧壁间隔物以覆盖扩散抑制区域的周边。然后执行第二导电类型的深体扩散，导致在侧壁间隔件之间的外延层中形成深体区。由第一和第二氧化物层的剩余部分覆盖的扩散抑制区域的周边阻止深体扩散的横向扩散，而不显着抑制扩散深度。

78. 发明授权

US5767578A Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation 失效
标题翻译：表面贴装和倒装芯片技术，具有金刚石膜钝化功能，可完全集成电路隔离
公开(公告)号：US5767578A
公开(公告)日：1998-06-16
申请号：US634957
申请日：1996-04-19
申请人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun , Hans-Jurgen Fusser , Reinhard Zachai
发明人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun , Hans-Jurgen Fusser , Reinhard Zachai
IPC分类号： H01L23/29 , H01L23/367 , H01L23/373 , H01L23/34
CPC分类号： H01L23/3672 , H01L23/29 , H01L23/3732 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/14
摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.
摘要翻译：集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。最初，芯片基板具有常规的厚度并且在其中形成半导体器件。在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。钝化层是提供电绝缘和导热性的CVD金刚石膜。去除衬底背面（通过研磨和/或CMP）以暴露沟槽的底部。这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。此后，漏极或集电极电触点设置在基板背面上。在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。然后将晶片以两种版本刻成模具，而不需要进一步的包装。

79. 发明授权

US5757081A Surface mount and flip chip technology for total integrated circuit isolation 失效
标题翻译：表面贴装和倒装芯片技术，用于全集成电路隔离
公开(公告)号：US5757081A
公开(公告)日：1998-05-26
申请号：US603512
申请日：1996-02-20
申请人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun
发明人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun
IPC分类号： H01L23/367 , H01L23/373 , H01L23/48
CPC分类号： H01L23/3672 , H01L23/3738 , H01L2224/16 , H01L2224/73253 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/14 , Y10S148/135 , Y10S438/928 , Y10S438/977
摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.
摘要翻译：集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。最初，芯片基板具有常规的厚度并且在其中形成半导体器件。在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。通过研磨或CMP去除衬底背面以露出沟槽的底部。这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。此后，漏极或集电极电触点设置在基板背面上。在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。然后将晶片刻成两个版本的模具，无需进一步包装。

80. 发明授权

US5753529A Surface mount and flip chip technology for total integrated circuit isolation 失效
公开(公告)号：US5753529A
公开(公告)日：1998-05-19
申请号：US444660
申请日：1995-05-19
申请人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun
发明人： Mike F. Chang , King Owyang , Fwu-Iuan Hshieh , Yueh-Se Ho , Jowei Dun
IPC分类号： H01L23/367 , H01L23/373 , H01L21/302
CPC分类号： H01L23/3672 , H01L23/3738 , H01L2224/16 , H01L2224/73253 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/14 , Y10S148/135 , Y10S438/928 , Y10S438/977
摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

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