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热词
    • 72. 发明授权
    • Data extracting circuit
    • 数据提取电路
    • US4385328A
    • 1983-05-24
    • US197606
    • 1980-10-16
    • Masato Tanaka
    • Masato Tanaka
    • G11B20/10H04L25/06H04L25/48G11B5/09
    • H04L25/062G11B20/10009
    • A data extracting circuit including an input terminal supplied with an input signal which is reproduced from a magnetic tape, positive and negative peak hold circuits connected to the input terminal, respectively, an adding circuit for adding the positive and negative peak voltages from the peak hold circuits at a predetermined rate and for producing a threshold voltage, and a level comparator having a first input terminal supplied with the delayed input signal and a second input terminal supplied with the threshold voltage and for deriving a digital binary data signal, the positive and negative peak hold circuits including a higher level priority circuit and a lower level priority circuit, respectively, and supplied with the input signal and a delayed signal which is further delayed by a second delay circuit following the delay circuit.
    • 一种数据提取电路,包括:输入端子,其被提供有从磁带再现的输入信号;正和负峰值保持电路,分别与输入端连接;加法电路,用于将来自峰值保持的正和负峰值电压相加; 以及用于产生阈值电压的电路;以及电平比较器,其具有被提供有延迟的输入信号的第一输入端和提供有阈值电压的第二输入端,并且用于导出数字二进制数据信号,所述正和负 峰值保持电路分别包括较高电平优先级电路和较低电平优先级电路,并提供有输入信号和延迟信号,该延迟信号由延迟电路之后的第二延迟电路进一步延迟。