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71. 发明授权

US07515499B2 Semiconductor memory device equipped with storage section for storing setting information to set initial operation and function 有权
标题翻译：半导体存储器件配备有用于存储设置信息以设置初始操作和功能的存储部分
公开(公告)号：US07515499B2
公开(公告)日：2009-04-07
申请号：US11609476
申请日：2006-12-12
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G11C8/00
CPC分类号： G11C16/10 , G11C16/3436
摘要： A device includes first and second memory cell arrays, first and second decoders, first and second sense amplifiers, and first and second switch circuits. The first switch circuit switches the supply of writing and erasing voltages or a reading voltage to the first memory cell array, and switches the supply of writing and erasing addresses or a reading address to the first decoder, and switches the connection of a data line connected to the first memory cell array to the first sense amplifier. The second switch circuit switches the supply of writing and easing voltages or a reading voltage to one of the second memory cell arrays, and switches the supply of writing and erasing addresses or a reading address to one of the second decoders, and switches the connection of a data line connected to the second memory cell arrays to the second sense amplifier.
摘要翻译：一种器件包括第一和第二存储单元阵列，第一和第二解码器，第一和第二读出放大器以及第一和第二开关电路。第一开关电路将写入和擦除电压的供给或读取电压切换到第一存储单元阵列，并将写入和擦除地址的供应或读取地址切换到第一解码器，并切换连接的数据线的连接到第一读出放大器的第一存储单元阵列。第二开关电路将写入和放宽电压的供给或读取电压切换到第二存储单元阵列之一，并将写入和擦除地址的供给或读取地址切换到第二解码器之一，并且切换连接到第二存储单元阵列到第二读出放大器的数据线。

72. 发明申请

US20080238866A1 Drawing circuit of electro-optical display device, drawing method of electro-optical display device, electro-optical display device, and electronic apparatus 审中-公开
标题翻译：电光显示装置的绘制电路，电光显示装置的绘制方法，电光显示装置和电子装置
公开(公告)号：US20080238866A1
公开(公告)日：2008-10-02
申请号：US12075885
申请日：2008-03-15
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G09G3/34
CPC分类号： G09G3/344 , G09G3/04 , G09G2300/08
摘要： Provided is a drawing device of an electro-optical display device which includes a drawing circuit for outputting image data to a driving circuit for driving electro-optical elements of a display unit for displaying an image based on the image data, and a control circuit for controlling the drawing circuit, wherein the drawing circuit includes a first memory in which a plurality of image material data is previously stored, a first working memory having a working area in which the image data composed of at least one image material data is generated, a second working memory having a command information area in which a command signal for instructing execution of a predetermined process is written, and a drawing control circuit which writes the command signal in the command information area and generates command information composed of a plurality of command signals in the command information area, and the control circuit outputs a first control command signal for executing the command information to the drawing control circuit.
摘要翻译：本发明提供一种电光显示装置的绘图装置，其包括：绘制电路，用于将图像数据输出到用于驱动基于图像数据显示图像的显示单元的电光元件的驱动电路;以及控制电路，控制绘图电路，其中绘图电路包括其中预先存储多个图像素材数据的第一存储器，具有生成由至少一个图像素材数据构成的图像数据的工作区域的第一工作存储器，第二工作存储器，其具有写入用于指示执行预定处理的命令信号的命令信息区;以及绘图控制电路，其将命令信号写入命令信息区域，并且生成由多个命令信号组成的命令信息命令信息区域和控制电路输出用于执行命令inf的第一控制命令信号绘图控制电路。

73. 发明申请

US20070183233A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20070183233A1
公开(公告)日：2007-08-09
申请号：US11669420
申请日：2007-01-31
申请人： Tomohito Kawano , Hidetoshi Saito
发明人： Tomohito Kawano , Hidetoshi Saito
IPC分类号： G11C29/00 , G11C16/06 , G11C11/34 , G11C7/00
CPC分类号： G11C29/34 , G11C16/04 , G11C2029/1204 , G11C2029/1802 , G11C2029/2602
摘要： There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.
摘要翻译：公开了一种具有用于写入的第一和第二负载电路的半导体集成电路器件。在所有位应力测试时，从第一和第二负载电路提供用于写入的高电压用于写入所有位线。在进行偶数位应力测试时，写入的高电压从第一负载电路提供给偶数位线，并且比写入的高电压低的电位从第二负载电路提供给写入奇数位线。在奇数位应力测试时，较低的电位从第一负载电路提供给偶数位线，并且用于写入的高电压从第二负载电路提供给奇数位线。

74. 发明授权

US07046559B2 Semiconductor memory device capable of erasing or writing data in one bank while reading data from another bank 失效
标题翻译：半导体存储器件能够在从另一个存储体读取数据的同时在一个存储体中擦除或写入数据
公开(公告)号：US07046559B2
公开(公告)日：2006-05-16
申请号：US10375116
申请日：2003-02-28
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/16 , G11C2216/22
摘要： There is disclosed a semiconductor memory device including a memory cell array containing a plurality of banks each having one or more blocks, a data erase circuit configured to erase data from selected blocks in banks at a unit of block, and an automatic multi-block erase circuit configured to enable a data read circuit configured to read data from memory cells provided in one bank, when data erase operation for all erase-object blocks in the one bank is completed, while continuing a data erasing operation of a next erase-object block included in another bank.
摘要翻译：公开了一种包括存储单元阵列的半导体存储器件，该存储单元阵列包含多个具有一个或多个块的存储体，数据擦除电路被配置为以块为单位从存储体中的所选块中擦除数据，以及自动多块擦除电路，被配置为当数据擦除操作对于一个存储单元中的所有擦除对象块完成时，使数据读取电路被配置为从设置在一个存储体中的存储单元读取数据，同时继续下一擦除对象块的数据擦除操作包括在另一家银行。

75. 发明授权

US06716161B2 Endoscope suitable for autoclave sterilization 失效
标题翻译：内窥镜适用于高压灭菌
公开(公告)号：US06716161B2
公开(公告)日：2004-04-06
申请号：US10097463
申请日：2002-03-13
申请人： Masakazu Higuma , Yasuyuki Futatsugi , Ichiro Nakamura , Yosuke Yoshimoto , Hidetoshi Saito , Susumu Aono , Takao Yamaguchi , Yutaka Tatsuno , Takahiro Kishi , Yasuhito Kura , Kazutaka Nakatsuchi , Takeaki Nakamura
发明人： Masakazu Higuma , Yasuyuki Futatsugi , Ichiro Nakamura , Yosuke Yoshimoto , Hidetoshi Saito , Susumu Aono , Takao Yamaguchi , Yutaka Tatsuno , Takahiro Kishi , Yasuhito Kura , Kazutaka Nakatsuchi , Takeaki Nakamura
IPC分类号： A61B104
CPC分类号： A61B1/00188 , A61B1/00195 , A61B1/121 , A61L2/07 , G02B23/2423 , G02B23/2453 , G02B23/26
摘要： An endoscope suitable for autoclave sterilization includes an insertion section having an objective lens section disposed at the extreme end thereof for focusing a subject image and an eyepiece section located on the base end side of the inserting section and including at least an eyepiece lens. an image guide fiber is disposed in the bundle for transmitting the subject image in an observation section focused by the objective lens section. An eyepiece lens unit is disposed in the eyepiece section, the eyepiece lens unit causing the eyepiece lens to confront the base end structure whose hermetic seal level is higher than the watertight seal level of the shell of the endoscope. A focus position changing means is disposed to the eyepiece lens unit to change the focus position of the eyepiece lens. The eyepiece section is so constructed and/or assembled that the autoclave sterilization process does not cause water vapor or the like to adversely affect the operability of the eyepiece section.
摘要翻译：适用于高压灭菌器的内窥镜包括：插入部，其具有设置在其前端的物镜部分，用于聚焦被摄体图像;以及目镜部分，位于插入部分的基端侧，并且至少包括目镜。图像引导光纤布置在用于在由物镜部分聚焦的观察部分中传送被摄体图像的束中。目镜透镜单元设置在目镜部分中，目镜透镜单元使目镜透镜面对密封水平高于内窥镜壳体的防水密封水平的基端结构。焦点位置改变装置设置在目镜透镜单元上以改变目镜透镜的对焦位置。目镜部分是如此构造和/或组装，使得高压灭菌器灭菌过程不会引起水蒸气等不利地影响目镜部分的可操作性。

76. 发明授权

US06452837B2 Nonvolatile semiconductor memory and threshold voltage control method therefor 失效
标题翻译：非易失性半导体存储器及其阈值电压控制方法
公开(公告)号：US06452837B2
公开(公告)日：2002-09-17
申请号：US09745802
申请日：2000-12-26
申请人： Seiichi Mori , Hiroyuki Sasaki , Hideo Kato , Hidetoshi Saito
发明人： Seiichi Mori , Hiroyuki Sasaki , Hideo Kato , Hidetoshi Saito
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： This invention discloses a memory cell threshold voltage shift method effective for the erase or write sequence of a nonvolatile semiconductor memory. First, the threshold voltages VTH of a plurality of memory cells are shifted at once to a range whose upper limit is set to an erase verify voltage VEV. After this, the lower limit of the threshold voltages VTH shifted at once to the range is shifted to a first overerase verify voltage VOEV1 close to the erase verify voltage VEV. Then, the lower limit of the threshold voltages VTH shifted to the first overerase verify voltage VOEV1 to a second overerase verify voltage VOEV2 closer to the erase verify voltage VEV.
摘要翻译：本发明公开了一种对非易失性半导体存储器的擦除或写入顺序有效的存储单元阈值电压偏移方法。首先，多个存储单元的阈值电压VTH一次移动到上限被设定为擦除验证电压VEV的范围。之后，将一度偏移到该范围的阈值电压VTH的下限移动到接近擦除验证电压VEV的第一过电压验证电压VOEV1。然后，将阈值电压VTH的下限移位到第一过电压验证电压VOEV1至接近擦除验证电压VEV的第二过电压验证电压VOEV2。

77. 发明授权

US6102976A Exhaust gas purifier 失效
标题翻译：废气净化器
公开(公告)号：US6102976A
公开(公告)日：2000-08-15
申请号：US81988
申请日：1998-05-21
申请人： Masataka Oji , Hidetoshi Saito , Shiro Nakajima , Satoru Okamoto
发明人： Masataka Oji , Hidetoshi Saito , Shiro Nakajima , Satoru Okamoto
IPC分类号： F01N3/02 , F01N3/027 , B01D46/00
CPC分类号： F01N3/027 , F01N2310/04 , Y10S55/10 , Y10S55/30
摘要： An exhaust gas purifier which can efficiently eliminate particulate matter discharged from an engine, and which has a long life. The purifier is attached to a discharge passage of an engine, and includes a filter constituted by a plurality of cylindrical filter elements each formed of porous metal. The filter elements are different in diameter from each other, and disposed concentrically and assembled radially apart from each other through a space. The filter has an exhaust gas inlet passage side end and an exhaust gas outlet passage side end, the exhaust gas inlet side end being closed, by a shielding plate, up to the cylindrical filter element of the largest outer diameter, and the exhaust gas outlet passage side end being closed at a portion between an outer circumferential case and the cylindrical filter element of the smallest outer diameter. The exhaust gas purifier further includes a plate-like heater disposed between the filter element of the largest outer diameter and the filter element disposed inside and adjacent to the filter element of the largest outer diameter without contacting with the two filter elements. Preferably, three-dimensional mesh porous metal having the same average pore-size is used as a material for each of the cylindrical filter elements.
摘要翻译：一种排气净化器，其能够有效地消除从发动机排出的颗粒物质，其寿命长。净化器附接到发动机的排出通道，并且包括由多个由多孔金属形成的多个圆柱形过滤元件构成的过滤器。过滤元件的直径彼此不同，并且同心地设置并且通过空间彼此径向组装。过滤器具有排气入口通道侧端部和废气出口通道侧端部，废气入口侧端部被遮蔽板封闭，直到最大外径的圆筒形过滤器元件，排气出口通道侧端部在外周壳体和最小外径的圆筒形过滤器元件之间的部分处封闭。排气净化器还包括设置在最大外径的过滤元件和设置在最大外径的过滤元件的内部并且与过滤元件相邻并且与两个过滤器元件接触的过滤元件之间的板状加热器。优选地，使用具有相同平均孔径的三维网孔多孔金属作为每个圆筒形过滤元件的材料。

78. 发明授权

US6094373A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US6094373A
公开(公告)日：2000-07-25
申请号：US31240
申请日：1998-02-26
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G11C16/02 , G11C16/10 , G11C16/16 , G11C29/12 , G11C16/06
CPC分类号： G11C16/10 , G11C16/16
摘要： This invention is made to reduce the circuit area and shorten the testing time by simplifying the construction of the control circuit and reducing the number of commands. In the automatic programming operation, PVOK is set to "0", EVOK and LCKOK are set to "1", and a memory cell is selected by an address latched in the address register. That is, the subroutine of a pre-program operation is effected with the address fixed. None of the subroutines of an erase operation and convergence operation are effected. In the erase operation, PVOK, EVOK and LCKOK are all set to "0" and memory cells are sequentially selected by the internal address of the address counter. That is, each of the memory cells selected by the internal address is subjected to the pre-program, erase and convergence operations.
摘要翻译：本发明是通过简化控制电路的结构和减少命令数来减少电路面积和缩短测试时间的。在自动编程操作中，PVOK设置为“0”，EVOK和LCKOK设置为“1”，并通过地址寄存器中锁存的地址选择存储单元。也就是说，预编程操作的子程序是以固定地址进行的。擦除操作和收敛操作的子程序都不实现。在擦除操作中，PVOK，EVOK和LCKOK都被设置为“0”，存储单元由地址计数器的内部地址依次选择。也就是说，由内部地址选择的每个存储单元经受预编程，擦除和收敛操作。

79. 发明授权

US5359894A Acceleration detector having highly accurate gaps in magnetic circuit including a differential transformer 失效
标题翻译：加速度检测器在包括差动变压器的磁路中具有高精度的间隙
公开(公告)号：US5359894A
公开(公告)日：1994-11-01
申请号：US851947
申请日：1992-03-13
申请人： Hidetoshi Saito , Masahiro Kume
发明人： Hidetoshi Saito , Masahiro Kume
IPC分类号： G01P15/11
CPC分类号： G01P15/11
摘要： An acceleration detector includes a magnetic body movable under acceleration, and a differential transformer having primary coils and secondary coils and arranged so that an output differential is produced between the secondary coils when the movable magnetic body is displaced. The movable magnetic body extends through the primary coils and the secondary coils and has opposite ends protruding from the coils. Leaf springs are provided to support the protruding ends of the movable magnetic body. The case comprises a cylindrical body surrounding the outer periphery of the differential transformer and lids closing openings of the body at both ends thereof. Between the lids and both ends of the movable body predetermined gaps are provided through which a magnetic flux can flow. The leaf springs are secured in position between end faces of the body and the lids.
摘要翻译：加速度检测器包括可加速移动的磁体和具有初级线圈和次级线圈的差动变压器，并且布置成当可移动磁体移位时在次级线圈之间产生输出差分。可动磁体延伸穿过初级线圈和次级线圈，并且具有从线圈突出的相对端。提供板簧以支撑可移动磁体的突出端。壳体包括围绕差动变压器的外周的圆柱形主体，并且在其两端封闭主体的开口。在可动体的盖子和两端之间提供预定的间隙，通过该间隙可以流过磁通量。板簧固定在主体的端面和盖子之间的位置。

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