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    • 76. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08824192B2
    • 2014-09-02
    • US13455475
    • 2012-04-25
    • Masami Endo
    • Masami Endo
    • G11C11/24
    • H01L27/1225H03K17/20
    • A semiconductor device that has a simple peripheral circuit configuration, is unlikely to deteriorate due to repetitive data writing operations, and is used as a nonvolatile switch. Even when supply of a power supply voltage is stopped, data on a conduction state is held in a data retention portion connected to a thin film transistor including an oxide semiconductor layer having a channel formation region. The data retention portion is connected to a gate of a field-effect transistor in a current amplifier circuit (in which the field-effect transistor and a bipolar transistor are connected as a Darlington pair), and thus the conduction state is controlled without leaking charge in the data retention portion.
    • 具有简单的外围电路配置的半导体器件由于重复的数据写入操作而不太可能劣化,并被用作非易失性开关。 即使停止供给电源电压,导通状态的数据被保持在连接到包括具有沟道形成区域的氧化物半导体层的薄膜晶体管的数据保持部分中。 数据保持部分连接到电流放大器电路中的场效应晶体管的栅极(其中场效应晶体管和双极晶体管作为达林顿对连接),因此导通状态被控制而不泄漏电荷 在数据保留部分中。
    • 77. 发明申请
    • MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT
    • 存储元件和信号处理电路
    • US20120230138A1
    • 2012-09-13
    • US13405422
    • 2012-02-27
    • Masami Endo
    • Masami Endo
    • G11C7/06G11C7/12
    • G11C7/06G11C7/12G11C14/0054G11C16/0441G11C19/184G11C19/28
    • A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.
    • 提供具有新颖结构的存储元件和包括存储元件的信号处理电路。 包括包括第一晶体管和第二晶体管的第一电路和包括第三晶体管和第四晶体管的第二电路。 分别对应于输入信号的第一信号电位和第二信号电位经由导通状态的第一晶体管分别输入到第二晶体管的栅极,并经由第三晶体管的导通 州。 之后,第一晶体管和第三晶体管截止。 使用第二晶体管和第四晶体管的状态来读出输入信号。 包括其中形成沟道的氧化物半导体的晶体管可以用于第一晶体管和第三晶体管。
    • 80. 发明授权
    • Display device and electronic device using the same
    • 显示装置和使用其的电子装置
    • US08159478B2
    • 2012-04-17
    • US11568892
    • 2005-09-26
    • Tadafumi OzakiMasami Endo
    • Tadafumi OzakiMasami Endo
    • G09G5/02
    • G09G3/3225G09G3/2022G09G5/399G09G2310/0227G09G2320/0247G09G2320/0285G09G2320/048
    • According to the invention, a compact and inexpensive with low power consumption memory and low access speed can be used for a panel controller and a deterioration compensation circuit of a display device. In a display device of a digital gray scale method, a plurality of pixels of a display panel are divided into first to n-th pixel regions (n is 2 or more) and a format converter portion of a panel controller converts the format of only video data corresponding to one of first to n-th pixel regions and writes the data to one of first and second video memories in each frame period. A display control portion reads out video data that is converted in format and corresponds to one of first to n-th pixel regions in which video data is written to the other of the first and second video memories in the preceding frame period, and transmits the data to the display panel.
    • 根据本发明,可以使用具有低功耗存储器和低访问速度的紧凑且便宜的面板控制器和显示装置的劣化补偿电路。 在数字灰度法的显示装置中,显示面板的多个像素被划分为第一至第n像素区域(n为2以上),面板控制器的格式转换器部分仅转换格式 对应于第一至第n像素区域之一的视频数据,并将数据写入每个帧周期中的第一和第二视频存储器之一。 显示控制部分读出在前一帧周期中以格式转换并对应于其中将视频数据写入第一和第二视频存储器中的另一个的第一至第n个像素区域之一的视频数据,并将其发送 数据到显示面板。