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71. 发明授权

US08293608B2 Intermediate product for a multichannel FET and process for obtaining an intermediate product 有权
标题翻译：用于多通道FET的中间产物和用于获得中间产物的方法
公开(公告)号：US08293608B2
公开(公告)日：2012-10-23
申请号：US12865517
申请日：2008-02-08
申请人： Marius Orlowski , Andreas Wild
发明人： Marius Orlowski , Andreas Wild
IPC分类号： H01L21/20
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66772 , H01L29/78687
摘要： An intermediate product in the manufacture of a vertical multiple-channel FET device containing alternating —Si—[(SiGe)—Si]u- stacked layers is shown, as well as a process for selectively etching the SiGe layers in such a stacked layer system, and products obtained from such selective etching. Differential Ge content is added to the successive layers to provide uniform removal of the sacrificial SiGe layers.
摘要翻译：示出了制造包含交替的-Si - [（SiGe）-Si]层叠层的垂直多通道FET器件的中间产品，以及用于在这种堆叠层系统中选择性蚀刻SiGe层的工艺，以及从这种选择性蚀刻获得的产品。将差分Ge含量添加到连续层中以提供牺牲SiGe层的均匀去除。

72. 发明授权

US08264060B2 Method of sealing an air gap in a layer of a semiconductor structure and semiconductor structure 有权
标题翻译：密封半导体结构和半导体结构层中的气隙的方法
公开(公告)号：US08264060B2
公开(公告)日：2012-09-11
申请号：US13300953
申请日：2011-11-21
申请人： Greg Braeckelmann , Marius Orlowski , Andreas Wild
发明人： Greg Braeckelmann , Marius Orlowski , Andreas Wild
IPC分类号： H01L21/00
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76834
摘要： Providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer. The air gap extends into the first layer from a first surface of the first layer. A barrier dielectric material over the first surface and the air gap is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. An air gap can extend from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces.
摘要翻译：提供在第一层中形成的导线之间具有至少一个气隙的半导体结构的第一层。气隙从第一层的第一表面延伸到第一层。选择第一表面和空气间隙上的阻挡介电材料以具有小于3.5的介电常数并提供屏障以防止化学品进入至少一个气隙。气隙可以从第一层的第一表面延伸到至少两个导电线的侧表面的至少一部分，以暴露侧表面的至少一部分。

73. 发明申请

US20120199879A1 METHOD OF FORMING AN INVERTED T SHAPED CHANNEL STRUCTURE FOR AN INVERTED T CHANNEL FIELD EFFECT TRANSISTOR DEVICE 有权
标题翻译：形成用于反相T通道场效应晶体管器件的反相T形通道结构的方法
公开(公告)号：US20120199879A1
公开(公告)日：2012-08-09
申请号：US13447369
申请日：2012-04-16
申请人： Marius Orlowski , Andreas Wild
发明人： Marius Orlowski , Andreas Wild
IPC分类号： H01L29/78
CPC分类号： H01L29/7854 , H01L29/66795 , H01L29/78687
摘要： A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.
摘要翻译：形成具有用于反向T沟道场效应晶体管ITFET器件的垂直沟道部分和水平沟道部分的反向T形沟道结构的方法包括半导体衬底，半导体衬底上的第一半导体材料的第一层和第二层在第一层上的第二半导体材料。选择第一和第二半导体材料，使得第一半导体材料具有小于除去第二半导体材料的速率的去除速率。

74. 发明授权

US07608893B2 Multi-channel transistor structure and method of making thereof 失效
标题翻译：多通道晶体管结构及其制造方法
公开(公告)号：US07608893B2
公开(公告)日：2009-10-27
申请号：US12037147
申请日：2008-02-26
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L23/62
CPC分类号： H01L29/1029 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.
摘要翻译：形成电子器件的方法包括：形成耦合到第一电流电极和第二电流电极并形成耦合到第一电流电极和第二电流电极的第二通道的第一通道。该方法还包括在第一平面内基本平行于第一通道的第二通道，其中第一平面平行于第一通道所在的基板的主表面。在第二平面中围绕第一通道和第二通道形成栅电极，其中第二平面垂直于衬底的主表面。所得到的半导体器件在每个位置具有多个具有多个通道的位置。在小尺寸下，通道形成连接源极和漏极的量子线。

75. 发明申请

US20080142853A1 MULTI-CHANNEL TRANSISTOR STRUCTURE AND METHOD OF MAKING THEREOF 失效
标题翻译：多通道晶体管结构及其制作方法
公开(公告)号：US20080142853A1
公开(公告)日：2008-06-19
申请号：US12037147
申请日：2008-02-26
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L29/80
CPC分类号： H01L29/1029 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.
摘要翻译：形成电子器件的方法包括：形成耦合到第一电流电极和第二电流电极并形成耦合到第一电流电极和第二电流电极的第二通道的第一通道。该方法还包括在第一平面内基本平行于第一通道的第二通道，其中第一平面平行于第一通道所在的基板的主表面。在第二平面中围绕第一通道和第二通道形成栅电极，其中第二平面垂直于衬底的主表面。所得到的半导体器件在每个位置具有多个具有多个通道的位置。在小尺寸下，通道形成连接源极和漏极的量子线。

76. 发明申请

US20070166902A1 Method to control the gate sidewall profile by graded material composition 有权
标题翻译：通过分级材料组成控制栅极侧壁轮廓的方法
公开(公告)号：US20070166902A1
公开(公告)日：2007-07-19
申请号：US11331958
申请日：2006-01-13
申请人： Marius Orlowski , Olubunmi Adetutu , Philllip Stout
发明人： Marius Orlowski , Olubunmi Adetutu , Philllip Stout
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.
摘要翻译：半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（36）上形成的栅极堆叠（30,32），由此形成具有垂直侧壁轮廓（35）的蚀刻栅极（33）。通过用硅基层的分级材料组成构造栅极堆叠（30,32），其组成被选择以抵消预定的图案化和蚀刻步骤的蚀刻趋势，更理想的垂直栅极侧壁轮廓（ 35）。

77. 发明申请

US20070158764A1 Electronic device including a fin-type transistor structure and a process for forming the electronic device 有权
标题翻译：包括鳍型晶体管结构的电子器件和用于形成电子器件的工艺
公开(公告)号：US20070158764A1
公开(公告)日：2007-07-12
申请号：US11328594
申请日：2006-01-10
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译：电子器件可以包括绝缘层和鳍型晶体管结构。翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。电介质层和间隔结构可以位于半导体鳍片和栅电极之间。半导体鳍片可以包括沟道区域，该沟道区域包括与相对较低V T T T相关的部分与绝缘层之间相对较高的V SUB相关联的部分。在一个实施例中，电源电压低于沟道区的相对较高的V SUB。还公开了一种用于形成电子器件的工艺。

78. 发明申请

US20070082453A1 METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM 有权
标题翻译：使用硅锗制备半导体结构的方法
公开(公告)号：US20070082453A1
公开(公告)日：2007-04-12
申请号：US11609664
申请日：2006-12-12
申请人： Marius Orlowski , Alexander Barr , Mariam Sadaka , Ted White
发明人： Marius Orlowski , Alexander Barr , Mariam Sadaka , Ted White
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供了具有硅层的半导体衬底。在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。在硅层上形成非晶或多晶硅锗层。或者，将锗注入硅层的顶部以形成非晶硅锗层。然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

79. 发明申请

US20070077706A1 Method of making a multi-bit nov-volatile memory (NYM) cell and structure 有权
标题翻译：制造多位非易失性存储器（NYM）单元和结构的方法
公开(公告)号：US20070077706A1
公开(公告)日：2007-04-05
申请号：US11240242
申请日：2005-09-30
申请人： Marius Orlowski , Sinan Goktepeli
发明人： Marius Orlowski , Sinan Goktepeli
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/42332
摘要： A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.
摘要翻译：多位非易失性存储单元包括第一浮栅侧壁间隔结构和与第一浮栅侧壁间隔结构物理分离的第二浮栅侧壁间隔结构。每个浮栅侧壁间隔结构存储逻辑存储位的电荷。通过从浮置栅极材料层（例如多晶硅）的侧壁间隔物形成工艺，将浮栅侧壁间隔结构形成为与图案化结构相邻。通过形成控制栅极材料层，然后对控制栅极材料层进行图案化，在浮栅侧壁间隔结构上形成控制栅极。

80. 发明申请

US20070072334A1 Semiconductor fabrication process employing spacer defined vias 审中-公开
标题翻译：半导体制造工艺采用间隔件定义的通孔
公开(公告)号：US20070072334A1
公开(公告)日：2007-03-29
申请号：US11239282
申请日：2005-09-29
申请人： Marius Orlowski , Kathleen Yu
发明人： Marius Orlowski , Kathleen Yu
IPC分类号： H01L21/00 , H01L21/8236
CPC分类号： H01L21/76835 , H01L21/76808 , H01L21/76811
摘要： A semiconductor fabrication process includes forming a first etch mask (131) that defines a first opening (132) and a second etch mask (140) that defines a second opening (142) overlying an interlevel dielectric (ILD) (108). The ILD (108) is etched to form a first via (154) defined by the first opening (132) and a second via (152) defined by the second opening (142). The first etch mask (131) may include a patterned hard mask layer (122) and the second etch mask may be a patterned photoresist layer (140). The first etch mask may further include spacers (130) adjacent sidewalls of the patterned hard mask layer (122). The patterned hard mask layer (122) may be a titanium nitride and the spacers (130) may be silicon nitride. The ILD (108) may be an CVD low-k dielectric layer overlying a CVD low-k etch stop layer (ESL) (106).
摘要翻译：半导体制造工艺包括形成限定第一开口（132）的第一蚀刻掩模（131）和限定覆盖层间电介质（IL））的第二开口（142）的第二蚀刻掩模（140）。蚀刻ILD（108）以形成由第一开口（132）限定的第一通孔（154）和由第二开口（142）限定的第二通孔（152）。第一蚀刻掩模（131）可以包括图案化的硬掩模层（122），并且第二蚀刻掩模可以是图案化的光致抗蚀剂层（140）。第一蚀刻掩模还可以包括与图案化的硬掩模层（122）的侧壁相邻的间隔物（130）。图案化的硬掩模层（122）可以是氮化钛，并且间隔物（130）可以是氮化硅。 ILD（108）可以是覆盖CVD低k蚀刻停止层（ESL）（106）的CVD低k电介质层。

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