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71. 发明授权

US07100151B2 Recovery from corruption using event offset format in data trace 有权
公开(公告)号：US07100151B2
公开(公告)日：2006-08-29
申请号：US10302024
申请日：2002-11-22
申请人： John M. Johnsen , Manisha Agarwala , Maria B. H. Gill
发明人： John M. Johnsen , Manisha Agarwala , Maria B. H. Gill
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/3652
摘要： A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is not a program counter sync point, then the trace transmits an indication of the current program counter address in an offset format from the program counter address of a last transmitted program counter sync point and then transmits trace data in event offset format. If the first trace data following detection of corruption is a program counter sync point, then the trace transmits trace data in event offset format.

72. 发明授权

US06948155B2 Little offset in multicycle event maintaining cycle accurate tracing of stop events 有权
标题翻译：在多周期事件保持周期中几乎没有偏移准确跟踪停止事件
公开(公告)号：US06948155B2
公开(公告)日：2005-09-20
申请号：US10301894
申请日：2002-11-22
申请人： Manisha Agarwala , Bryan Thome , Gary L. Swoboda
发明人： Manisha Agarwala , Bryan Thome , Gary L. Swoboda
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： A method of tracing activity of a data processor includes collecting and transmitting trace data. An epause marker is embedded in the trace stream upon detection of an emulation halt. This epause marker includes a little offset indicating a number of latency instructions within trace collection hardware since a program counter exception. This permits the utilization emulation device to annulling trace data corresponding to the latency instructions.
摘要翻译：跟踪数据处理器的活动的方法包括收集和发送跟踪数据。在检测到仿真停止时，暂停标记被嵌入到跟踪流中。该暂停标记包括一个偏移量，指示跟踪收集硬件中的一个延迟指令数，因为程序计数器异常。这允许利用率仿真设备取消对应于等待时间指令的跟踪数据。

73. 发明授权

US5338983A Application specific exclusive of based logic module architecture for FPGAs 失效
标题翻译：专用于FPGA的基于逻辑模块架构的应用
公开(公告)号：US5338983A
公开(公告)日：1994-08-16
申请号：US166330
申请日：1993-12-10
申请人： Manisha Agarwala
发明人： Manisha Agarwala
IPC分类号： G06F7/00 , G06F7/50 , G06F7/501 , H03K19/173 , H03K19/177
CPC分类号： G06F7/501 , H03K19/1736 , G06F2207/4812
摘要： A logic module (20) includes five input terminals (a-e), two output terminals (F1, F2), and control logic (22, 24, 26, 28, 30, 32, 36) for selectively coupling one or more of the input terminals to one of the output terminals. First and second input terminals (a, b) are connected to inputs of a first XOR gate (22); a third input terminal (c) is connected to one input of a multiplexor (24) through an inverter (26); a fourth input terminal (d) is connected to the other input of the multiplexor (24) and to one input of a first NAND gate (28); and a fifth input terminal (e) is connected to one input of a second XOR gate (30) and to one input of a second NAND gate (32). The first XOR gate (22) has its output connected to the other input of the first NAND gate (28) and to the control input of the multiplexor (24). The output of the multiplexor (24) is connected to the other inputs of the second XOR gate (30) and second NAND gate (32). The outputs of the first and second NAND gates (28, 32) are connected to the inputs of a third NAND gate (36). The outputs of the third NAND gate (36) and second XOR gate (30) are the output terminals (F2, F1) of the logic module (10). The configuration of the logic module (20) permits implementation of adders and subtractors for DSPs with only one logic module.
摘要翻译：逻辑模块（20）包括五个输入端（ae），两个输出端（F1，F2）和控制逻辑（22,24,26,28,30,32,36），用于选择性地耦合一个或多个输入端子到其中一个输出端子。第一和第二输入端子（a，b）连接到第一异或门（22）的输入端; 第三输入端（c）通过反相器（26）连接到多路复用器（24）的一个输入端; 第四输入端（d）连接到多路复用器（24）的另一输入端和第一NAND门（28）的一个输入端; 和第五输入端（e）连接到第二异或门（30）的一个输入端和第二与非门（32）的一个输入端。第一异或门（22）的输出端连接到第一与非门（28）的另一个输入端和多路复用器（24）的控制输入端。多路复用器（24）的输出端连接到第二异或门（30）和第二与非门（32）的其它输入端。第一与非门（28,32）的输出端连接到第三与非门（36）的输入端。第三与非门（36）和第二异或门（30）的输出是逻辑模块（10）的输出端子（F2，F1）。逻辑模块（20）的配置允许仅使用一个逻辑模块来实现DSP的加法器和减法器。

74. 发明授权

US08881114B2 Stored program writing stall information when a processor stalls waiting for another processor 有权
标题翻译：当处理器停止等待另一个处理器时，存储程序写入停止信息
公开(公告)号：US08881114B2
公开(公告)日：2014-11-04
申请号：US11383469
申请日：2006-05-15
申请人： Oliver P. Sohm , Brian Cruickshank , Manisha Agarwala , Gary L. Swoboda
发明人： Oliver P. Sohm , Brian Cruickshank , Manisha Agarwala , Gary L. Swoboda
IPC分类号： G06F9/44
CPC分类号： G06F13/00 , G06F9/30098 , G06F9/30145 , G06F11/3471 , G06F11/3648
摘要： A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.
摘要翻译：插入用于将跟踪数据相关联的标记值的方法和系统在处理器核之间。至少一些说明性实施例是集成电路设备，其包括第一处理器核心，第一数据收集部分，其耦合到第一处理器核心并且被配置为收集包括由第一处理器核心执行的指令的地址的数据;第二处理器核心，以及耦合到第一处理器核心并被配置为收集包括由第二处理器核执行的指令的地址的数据的第二数据收集部分。集成电路设备被配置为将标记值插入到第一和第二处理器核心的数据中，这允许数据相关，使得同时执行的指令是可识别的。

75. 发明授权

US08832318B2 Dynamic data trace output scheme 有权
标题翻译：动态数据跟踪输出方案
公开(公告)号：US08832318B2
公开(公告)日：2014-09-09
申请号：US11563821
申请日：2006-11-28
申请人： Manisha Agarwala , Maria B. H. Gill , John M. Johnsen
发明人： Manisha Agarwala , Maria B. H. Gill , John M. Johnsen
IPC分类号： G06F15/16 , G06F11/36
CPC分类号： G06F11/3636 , G06F11/3656
摘要： Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.
摘要翻译：生成跟踪目标处理器活动的数据流。当多个流打开时，它们会在不同的时间被写入其各自的FIFO。对于特定的流，可能导出的数据的长度和字段可能不同。本发明是仅发出相关领域的方案。

76. 发明授权

US07607047B2 Method and system of identifying overlays 有权
标题翻译：识别覆盖物的方法和系统
公开(公告)号：US07607047B2
公开(公告)日：2009-10-20
申请号：US11383468
申请日：2006-05-15
申请人： Gary L. Swoboda , Oliver P. Sohm , Brian Cruickshank , Manisha Agarwala
发明人： Gary L. Swoboda , Oliver P. Sohm , Brian Cruickshank , Manisha Agarwala
IPC分类号： G06F11/00
CPC分类号： G06F11/3644 , G06F11/3648
摘要： A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of overlay programs), obtaining values indicative of which of the plurality of overlays of the traced program has executed on the target system, and displaying on a display device an indication of a proportion of an execution time on the processor of the target system dedicated to each of the plurality of overlay programs.
摘要翻译：识别叠加层的方法和系统。示例性实施例中的至少一些是包括在目标系统（跟踪的程序包括多个覆盖程序）上执行跟踪的程序的方法，获得指示跟踪的程序的多个覆盖中哪一个在目标系统上执行的值并且在显示装置上显示专用于多个重叠程序中的每一个的目标系统的处理器上的执行时间的比例的指示。

77. 发明授权

US07574586B2 Efficient transfer of branch information 有权
标题翻译：有效转移分支信息
公开(公告)号：US07574586B2
公开(公告)日：2009-08-11
申请号：US11383688
申请日：2006-05-16
申请人： Manisha Agarwala , John M. Johnsen
发明人： Manisha Agarwala , John M. Johnsen
IPC分类号： G06F9/00
CPC分类号： G06F11/3636
摘要： A system comprising a processor adapted to execute software code comprising branch instructions and a trace logic coupled to the processor and adapted to generate a branch packet comprising branch bits. At least some of the branch bits are associated with branch instructions executed by the processor. The trace logic flushes invalid branch bits in the branch packet with a common bit, the common bit an inverse of a valid branch bit. The trace logic outputs the branch packet with an indicator comprising the valid branch bit.
摘要翻译：一种包括处理器的系统，其适于执行包括分支指令的软件代码和耦合到所述处理器的跟踪逻辑，并适于生成包括分支位的分支分组。至少一些分支位与由处理器执行的分支指令相关联。跟踪逻辑以公共位刷新分支分组中的无效分支位，公共位是有效分支位的反向。跟踪逻辑输出具有包括有效分支位的指示符的分支分组。

78. 发明申请

US20070271448A1 MERGING BRANCH INFORMATION WITH SYNC POINTS 有权
标题翻译：合并分支信息与同步点
公开(公告)号：US20070271448A1
公开(公告)日：2007-11-22
申请号：US11383678
申请日：2006-05-16
申请人： Manisha Agarwala
发明人： Manisha Agarwala
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/3632
摘要： A method comprises determining whether a sync point is to be generated concurrent with a branch instruction and generating said sync point to include a program counter value and to indicate that the sync point occurred concurrent with the branch instruction.
摘要翻译：一种方法包括确定同步点是否将与分支指令同时产生，并且生成所述同步点以包括程序计数器值并且指示同步点与分支指令同时发生。

79. 发明申请

US20070271447A1 EFFICIENT TRANSFER OF BRANCH INFORMATION 有权
标题翻译：分支信息的有效转移
公开(公告)号：US20070271447A1
公开(公告)日：2007-11-22
申请号：US11383688
申请日：2006-05-16
申请人： Manisha Agarwala , John M. Johnsen
发明人： Manisha Agarwala , John M. Johnsen
IPC分类号： G06F9/44
CPC分类号： G06F11/3636
摘要： A system comprising a processor adapted to execute software code comprising branch instructions and a trace logic coupled to the processor and adapted to generate a branch packet comprising branch bits. At least some of the branch bits are associated with branch instructions executed by the processor. The trace logic flushes invalid branch bits in the branch packet with a common bit, the common bit an inverse of a valid branch bit. The trace logic outputs the branch packet with an indicator comprising the valid branch bit.
摘要翻译：一种包括处理器的系统，其适于执行包括分支指令的软件代码和耦合到所述处理器的跟踪逻辑，并适于生成包括分支位的分支分组。至少一些分支位与由处理器执行的分支指令相关联。跟踪逻辑以公共位刷新分支分组中的无效分支位，公共位是有效分支位的反向。跟踪逻辑输出具有包括有效分支位的指示符的分支分组。

80. 发明授权

US07162411B2 Dynamic data trace output scheme 有权
标题翻译：动态数据跟踪输出方案
公开(公告)号：US07162411B2
公开(公告)日：2007-01-09
申请号：US10302026
申请日：2002-11-22
申请人： Manisha Agarwala , Maria B. H. Gill , John M. Johnsen
发明人： Manisha Agarwala , Maria B. H. Gill , John M. Johnsen
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F11/3636 , G06F11/3656
摘要： Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.
摘要翻译：生成跟踪目标处理器活动的数据流。当多个流打开时，它们会在不同的时间被写入其各自的FIFO。对于特定的流，可能导出的数据的长度和字段可能不同。本发明是仅发出相关领域的方案。

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