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71. 发明授权

US07236856B2 Operation-assisting system and operation-assisting computer program 有权
公开(公告)号：US07236856B2
公开(公告)日：2007-06-26
申请号：US11506872
申请日：2006-08-21
申请人： Keiko Abe , Yasushi Harada , Masahiro Watanabe , Shouji Matsuzaki , Shinichirou Nakanami , Noriyuki Murakoshi
发明人： Keiko Abe , Yasushi Harada , Masahiro Watanabe , Shouji Matsuzaki , Shinichirou Nakanami , Noriyuki Murakoshi
IPC分类号： G05D11/00
CPC分类号： G06Q10/06 , F01K13/02 , F01K17/025 , G06Q50/06 , Y02E20/14 , Y02P80/11
摘要： An operation assisting system enhances the operator's willingness to participate in energy-saving efforts. The operation assisting system stores information about the actual operation of operated equipment carried out by the operator, evaluates the stored operation information, and displays the results of evaluation. The evaluation results relate to the cost concerning the operated equipment, the cost of supplying energy to the operation target facility, the cost concerning the operated equipment, the amount of emission of carbon dioxide, nitride oxide, and global warming substances, the amount of primary energy consumption, the crude oil-converted amount of energy consumption, the amount of excess or shortage of supply of energy, or electric power quality.

72. 发明申请

US20060023488A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060023488A1
公开(公告)日：2006-02-02
申请号：US11165404
申请日：2005-06-24
申请人： Shinichi Yasuda , Keiko Abe
发明人： Shinichi Yasuda , Keiko Abe
IPC分类号： G11C11/00
CPC分类号： G11C11/14
摘要： A semiconductor memory includes: a first node and a second node; a first MIS transistor, having first conductive carrier flows, including a source electrode connected to a first power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; a second MIS transistor, having second conductive carrier flows, including a source electrode connected to a second power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; and a resistance change element connected between the first node and the second node and having a variable resistance due to the direction in which a voltage is applied, wherein information is written in the resistance change element by applying a voltage between the first and the second node, and stored information is read out by applying a low or high input voltage to the first node and reading out a voltage difference in the second node.
摘要翻译：半导体存储器包括：第一节点和第二节点; 具有第一导电载流子的第一MIS晶体管，包括连接到第一电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 具有第二导电载流子的第二MIS晶体管，包括连接到第二电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 以及连接在第一节点和第二节点之间并且由于施加电压的方向而具有可变电阻的电阻变化元件，其中通过在第一和第二节点之间施加电压将信息写入电阻变化元件并且通过向第一节点施加低或高输入电压并读出第二节点中的电压差来读出存储的信息。

73. 发明授权

US06347180B1 Signal processor 有权
标题翻译：信号处理器
公开(公告)号：US06347180B1
公开(公告)日：2002-02-12
申请号：US09194897
申请日：1998-12-04
申请人： Hiroki Kotani , Keiko Abe
发明人： Hiroki Kotani , Keiko Abe
IPC分类号： H04N592
CPC分类号： G11B27/034 , G11B27/031 , G11B2220/2525 , G11B2220/41 , G11B2220/415 , H04N5/222
摘要： Inputted video signals are highly compressed in a high-compression processing means and the compressed signals are saved in a high-compression system processing means, and the video signals lowly compressed in a low-compression processing means and the compressed signals are saved in a first and a second recording means with separating them according to using frequency. The saved videos in the high-compression system processing means are edited and an executing sequence list showing their executing sequence is formed, and a video signal having a high using frequency is outputted from the first memory means which has a small storage capacity (thus, easily accessible), based on the executing sequence list.
摘要翻译：输入视频信号在高压缩处理装置中被高度压缩，并且压缩信号被保存在高压缩系统处理装置中，并且以低压缩处理装置低压缩的视频信号，并且将压缩信号保存在第一以及根据使用频率分离它们的第二记录装置。编辑高压缩系统处理装置中保存的视频，并且形成表示其执行顺序的执行顺序列表，并且从具有小存储容量的第一存储装置输出具有高使用频率的视频信号（因此，易于访问），基于执行顺序列表。

74. 发明授权

US06324467B1 Information providing system 失效
标题翻译：信息提供系统
公开(公告)号：US06324467B1
公开(公告)日：2001-11-27
申请号：US09518908
申请日：2000-03-03
申请人： Kimiyoshi Machii , Kazuyoshi Koga , Shigeru Matsuo , Yoshitaka Atarashi , Soshiro Kuzunuki , Keiko Abe , Toshimi Yokota
发明人： Kimiyoshi Machii , Kazuyoshi Koga , Shigeru Matsuo , Yoshitaka Atarashi , Soshiro Kuzunuki , Keiko Abe , Toshimi Yokota
IPC分类号： G01C2100
CPC分类号： G08G1/096811 , G01C21/32 , G01C21/3655 , G08G1/096816 , G08G1/096822 , G08G1/096838 , G08G1/096861 , G08G1/096894
摘要： An information providing system is capable of rendering map-information services even if the size of a free area in a memory employed in a terminal becomes small, disallowing all details of a map to be downloaded. A server employed in the information providing system has a search engine for searching a map data base for a map suitable for a destination and the present position of the terminal as received from the terminal, a route computing unit for computing a guide route from the present position to the destination, a map display location determination unit for determining a location at which route information including a map based on the calculated guide route is to be transmitted to the terminal and a thinning determination unit for thinning the information to be transmitted based on information on the terminal received from the terminal. The thinning determination unit has a priority-level definition table for defining priority levels assigned to map elements stored in the map data base.
摘要翻译：即使终端中使用的存储器中的空闲区域的大小变小，信息提供系统也能够呈现地图信息服务，不允许下载地图的所有细节。在信息提供系统中使用的服务器具有搜索引擎，用于在从地图数据库中搜索适合于目的地的地图和从终端接收到的终端的当前位置;路线计算单元，用于从当前计算引导路线位置到目的地，地图显示位置确定单元，用于基于所计算的引导路线将包括地图的路线信息的位置确定到终端;以及间隔确定单元，用于基于信息来稀疏要发送的信息在从终端接收的终端上。稀疏确定单元具有用于定义分配给存储在地图数据库中的地图元素的优先级的优先级级别定义表。

75. 发明授权

US10209313B2 Accumulator device, and state of charge evaluation apparatus and method for accumulator 有权
公开(公告)号：US10209313B2
公开(公告)日：2019-02-19
申请号：US13059891
申请日：2010-06-22
申请人： Keiko Abe , Yasuhiro Kobayashi , Masahiro Watanabe , Hisaaki Takabayashi , Yoshikazu Hirose
发明人： Keiko Abe , Yasuhiro Kobayashi , Masahiro Watanabe , Hisaaki Takabayashi , Yoshikazu Hirose
IPC分类号： G06F19/00 , G01R31/36
摘要： An accumulator and state of charge evaluation method for preparing, during charging and discharging, models for each of deterioration degrees, each representing a relationship between terminal voltage, current and state of charge, for selecting respective models for the times during charging and discharging in accordance with a total charging/discharging amount (Ah), a deterioration degree or an elapsed time of an operation of the accumulator, for further estimating state of charge from current accumulation, and for determining a final state of charge from estimated states of charge including a present state of charge estimated from the models for the times during charging and discharging of the accumulator, while using a time or a total charging/discharging amount (Ah) from a time of full-charging by equal charging of the accumulator up to present time to determine the final state of charge from the plurality of states of charge.

76. 发明授权

US08578318B2 Method for implementing circuit design for integrated circuit and computer readable medium 失效
标题翻译：集成电路和计算机可读介质电路设计实现方法
公开(公告)号：US08578318B2
公开(公告)日：2013-11-05
申请号：US13561483
申请日：2012-07-30
申请人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
发明人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5031 , G06F17/5054 , G06F17/5081
摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.
摘要翻译：在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线长度。

77. 发明授权

US08552763B2 Switch array including active regions being adjacent to each other in channel width direction of memory cell transistor 失效
标题翻译：开关阵列包括在存储单元晶体管的沟道宽度方向上彼此相邻的有源区
公开(公告)号：US08552763B2
公开(公告)日：2013-10-08
申请号：US13206730
申请日：2011-08-10
申请人： Keiko Abe
发明人： Keiko Abe
IPC分类号： H03K19/173
CPC分类号： H01L27/11521 , H01L27/11519 , H01L27/11565 , H01L27/11568
摘要： According to one embodiment, a switch array includes first and second switches provided in a switch unit. The first switch includes first and second memory cell transistors and a first pass transistor. A second switch includes third and fourth memory cell transistors and a second pass transistor. The first and second memory cell transistor is provided in a first active region. The first pass transistor is provided in a second active region in the substrate. The third and fourth memory cell transistor is provided in the first active region. The second pass transistor is provided in the second active region adjacent to the first pass transistor in the channel length direction. The first and second active regions are adjacent to each other in a channel width direction.
摘要翻译：根据一个实施例，开关阵列包括设置在开关单元中的第一和第二开关。第一开关包括第一和第二存储单元晶体管和第一传输晶体管。第二开关包括第三和第四存储单元晶体管和第二传输晶体管。第一和第二存储单元晶体管设置在第一有源区中。第一传输晶体管设置在衬底中的第二有源区中。第三和第四存储单元晶体管设置在第一有源区中。第二传输晶体管设置在沟道长度方向上与第一传输晶体管相邻的第二有源区中。第一和第二有源区域在沟道宽度方向上彼此相邻。

78. 发明授权

US08535977B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08535977B2
公开(公告)日：2013-09-17
申请号：US13369427
申请日：2012-02-09
申请人： Keiko Abe
发明人： Keiko Abe
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541
摘要： According to one embodiment, a semiconductor device manufacturing method includes producing a first substrate with an electrode, producing a second substrate with a through hole, stacking the second substrate on the first substrate, with an insulating layer intervening between the first substrate and the second substrate, making a hole reaching the electrode in the insulating layer under the through hole by etching the insulating layer with the second substrate as a mask, and filling the through hole and the hole with conductive substance.
摘要翻译：根据一个实施例，一种半导体器件制造方法包括：制造具有电极的第一衬底，产生具有通孔的第二衬底，将第二衬底堆叠在第一衬底上，绝缘层介于第一衬底和第二衬底之间通过用第二基板作为掩模蚀刻绝缘层，在通孔下方的绝缘层中到达电极的孔，并且用导电物质填充通孔和孔。

79. 发明申请

US20120315652A1 SWEET TASTE RECEPTOR-EXPRESSING CONSTRUCT, CELL BODY EXPRESSING THE SAME, AND UTILIZATION THEREOF 有权
标题翻译：甜味剂受体表达构造，表达其的细胞体及其利用
公开(公告)号：US20120315652A1
公开(公告)日：2012-12-13
申请号：US13512683
申请日：2010-09-08
申请人： Keiko Abe , Takumi Misaka , Takamasa Imada , Satoshi Fujiwara
发明人： Keiko Abe , Takumi Misaka , Takamasa Imada , Satoshi Fujiwara
IPC分类号： C12N15/85 , G01N33/566 , C12N5/10
CPC分类号： C07K14/705 , G01N33/5308 , G01N2333/705 , G01N2400/00
摘要： [Object] An object of the present invention is to provide a sweet taste receptor-expressing construct which can functionally stably express both of a sweet taste receptor (T1R2+T1R3) and a G protein α subunit at a high expression efficacy, and a stable expression cell body expressing the construct.[Solution] The sweet taste receptor-expressing construct of the present invention is such that respective genes encoding sweet taste receptor subunits T1R2 and T1R3, and a G protein α subunit are inserted into the same plasmid. The cell body of the present invention is such that the sweet taste receptor-expressing construct of the present invention is gene-introduced into a 293 cell in which an FRT (Flippase Recognition Target) sequence is incorporated into one place in a genome, to express sweet taste receptor subunits T1R2 and T1R3, and a G protein α subunit simultaneously.
摘要翻译：本发明的目的是提供一种能够以高表达效力功能稳定地表达甜味受体（T1R2 + T1R3）和G蛋白α亚基两者的甜味受体表达构建体，并且稳定地表达表达该构建体的表达细胞体。 [解决方案]本发明的甜味受体表达构建体将编码甜味受体亚基T1R2和T1R3的各基因和G蛋白α亚基插入同一质粒。本发明的细胞体是将本发明的甜味受体表达构建体的基因引入到将基因组中一个位置并入FRT（Flippase Recognition Target）序列的293细胞中，以表达甜味受体亚基T1R2和T1R3，以及G蛋白α亚基。

80. 发明授权

US08243498B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08243498B2
公开(公告)日：2012-08-14
申请号：US12884452
申请日：2010-09-17
申请人： Keiko Abe , Shinobu Fujita
发明人： Keiko Abe , Shinobu Fujita
IPC分类号： G11C11/00
CPC分类号： G11C14/009 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/21 , G11C14/0054 , G11C14/0081
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter.
摘要翻译：根据一个实施例，半导体集成电路包括第一和第二反相器，具有连接到字线的栅极的第一晶体管，连接到第一位线的源极和连接到第二反相器的输入端子的漏极，第二晶体管，其具有连接到字线的栅极，连接到第二位线的源极和连接到第一反相器的输入端子的漏极;第一可变电阻元件，其具有连接到第一位线的漏极的第一端子第一晶体管和连接到第一反相器的输出端的第二端子，以及第二可变电阻元件，其具有连接到第二晶体管的漏极的第一端子，以及连接到第二晶体管的输出端子的第二端子逆变器。

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