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71. 发明申请

US20070103350A1 Methods and apparatus for testing an integrated circuit 失效
标题翻译：用于测试集成电路的方法和装置
公开(公告)号：US20070103350A1
公开(公告)日：2007-05-10
申请号：US11272589
申请日：2005-11-10
申请人： Louis Hsu , Jack Mandelman , Joseph Marsh , Steven Zier
发明人： Louis Hsu , Jack Mandelman , Joseph Marsh , Steven Zier
IPC分类号： H03M1/10
CPC分类号： H03M1/1076
摘要： In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供一种测试模拟电路的方法。该方法包括（1）向模拟电路提供一种适合于使模拟电路在测试期间像逻辑门一样起作用的屏蔽电路; 和（2）将数字信号施加到模拟电路以在晶片级测试模拟电路，以便检测模拟电路的一个或多个部件中的缺陷。提供了许多其他方面。

72. 发明申请

US20070103173A1 Systems and Methods for Controlling of Electro-Migration 有权
标题翻译：控制电迁移的系统和方法
公开(公告)号：US20070103173A1
公开(公告)日：2007-05-10
申请号：US11566796
申请日：2006-12-05
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R27/08
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

73. 发明申请

US20070099326A1 eFuse and methods of manufacturing the same 有权
标题翻译： eFuse及其制造方法
公开(公告)号：US20070099326A1
公开(公告)日：2007-05-03
申请号：US11266740
申请日：2005-11-03
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是eFuse，包括（1）衬底的绝缘氧化物层上方的半导体层; （2）形成在半导体层中的二极管; 和（3）二极管上形成的硅化物层。提供了许多其他方面。

74. 发明申请

US20070057325A1 Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures 有权
标题翻译：具有封装的栅电极的半导体FinFET结构和用于形成这种半导体FinFET结构的方法
公开(公告)号：US20070057325A1
公开(公告)日：2007-03-15
申请号：US11225654
申请日：2005-09-13
申请人： Louis Hsu , Jack Mandelman
发明人： Louis Hsu , Jack Mandelman
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.
摘要翻译：其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。

75. 发明申请

US20070018239A1 Sea-of-fins structure on a semiconductor substrate and method of fabrication 审中-公开
标题翻译：半导体衬底上的海鳍结构和制造方法
公开(公告)号：US20070018239A1
公开(公告)日：2007-01-25
申请号：US11185646
申请日：2005-07-20
申请人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
发明人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
IPC分类号： H01L29/76
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L27/1211 , H01L29/66795 , H01L29/66803 , H01L29/785 , Y10S977/734 , Y10S977/742 , Y10S977/749 , Y10S977/815 , Y10S977/955
摘要： A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.
摘要翻译：一种半导体器件和半导体器件的制造方法，其中所述方法包括在衬底上形成多个用于定制鳍状场效应晶体管（FinFET）器件形成的平坦化翅片体; 在所述多个翅片体中的每一个周围形成氮化物间隔物; 在每个翅片体之间形成隔离区域; 并用保护膜涂覆多个翅片体，氮化物间隔物和隔离区域。制造的半导体器件适用于定制应用中作为定制的半导体器件。

76. 发明申请

US20060145356A1 ON-CHIP COOLING 审中-公开
标题翻译：片上冷却
公开(公告)号：US20060145356A1
公开(公告)日：2006-07-06
申请号：US10905478
申请日：2005-01-06
申请人： Hsichang Liu , Louis Hsu , William Tonti
发明人： Hsichang Liu , Louis Hsu , William Tonti
IPC分类号： H01L23/52
CPC分类号： H01L23/467 , H01L23/36 , H01L25/0657 , H01L2224/16 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A method and structure for forming an integrated circuit chip that forms thermal conductors in a second wafer, and bonds the second wafer to a first wafer. Then circuits are formed in the first wafer. The thermal conductors in the second wafer have a higher coefficient of thermal conductivity than the second wafer and the bonding process seals the thermal conductors within the second wafer. Chip carrier connections are formed on the side of the first wafer that is opposite to the side where the first wafer is bonded to the second wafer, and then the first wafer can be bonded to a chip carrier. The second wafer has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the first wafer.
摘要翻译：一种用于形成在第二晶片中形成热导体并将第二晶片结合到第一晶片的集成电路芯片的方法和结构。然后在第一晶片中形成电路。第二晶片中的热导体具有比第二晶片更高的导热系数，并且接合工艺密封第二晶片内的热导体。芯片载体连接形成在第一晶片的与第一晶片接合到第二晶片的一侧相反的一侧，然后第一晶片可以结合到芯片载体上。第二晶片具有与第一晶片的热膨胀系数匹配的热膨胀系数。

77. 发明授权

US07060546B2 Ultra-thin SOI MOSFET method and structure 失效
标题翻译：超薄SOI MOSFET方法及结构
公开(公告)号：US07060546B2
公开(公告)日：2006-06-13
申请号：US10707200
申请日：2003-11-26
申请人： Louis Hsu , Carl J. Radens , Ramachandra Divakaruni
发明人： Louis Hsu , Carl J. Radens , Ramachandra Divakaruni
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/66772 , H01L21/76283 , H01L29/458 , H01L29/66545
摘要： An ultra-thin, scaleable MOSFET transistor and fabrication method are described. The transistor features fully self-aligned, raised source/drain junctions on a thin SOI wafer and exhibits low contact resistance, low gate resistance and good device isolation characteristic. No extra lithographic mask steps are required beyond those required by conventional processes. The transistor is completely “bracketed” or surrounded by STI (shallow trench isolation), providing inherent isolation between it and any other devices on the SOI wafer. Gate sidewall spacers are formed outside of the gate area so that the scalability is limited solely by lithography resolution.
摘要翻译：描述了一种超薄的可扩展MOSFET晶体管和制造方法。晶体管在薄SOI晶圆上具有完全自对准的升高的源极/漏极结，并且具有低接触电阻，低栅极电阻和良好的器件隔离特性。不需要额外的光刻掩模步骤，超出传统工艺所需要的步骤。晶体管完全“包围”或被STI（浅沟槽隔离）包围，提供了SOI晶片上任何其他器件之间的固有隔离。栅极侧壁间隔物形成在栅极区域的外部，从而可扩展性仅由光刻分辨率限制。

78. 发明申请

US20060043435A1 Nano-scaled gate structure with self-interconnect capabilities 失效
公开(公告)号：US20060043435A1
公开(公告)日：2006-03-02
申请号：US10930989
申请日：2004-08-31
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.

79. 发明申请

US20060014356A1 Metal-insulator-metal capacitor and method of fabricating same 有权
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US20060014356A1
公开(公告)日：2006-01-19
申请号：US11205719
申请日：2005-08-17
申请人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
发明人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少在第一绝缘层中形成第一开口和至少第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

80. 发明申请

US20050266652A1 HIGH DENSITY MIMCAP WITH A UNIT REPEATABLE STRUCTURE 失效
标题翻译：具有单位重复结构的高密度MIMCAP
公开(公告)号：US20050266652A1
公开(公告)日：2005-12-01
申请号：US10709768
申请日：2004-05-27
申请人： Michael Chudzik , Louis Hsu , Joseph Shepard , William Tonti
发明人： Michael Chudzik , Louis Hsu , Joseph Shepard , William Tonti
IPC分类号： H01L21/02 , H01L21/8242 , H01L23/522
CPC分类号： H01L28/91 , H01L23/5223 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.
摘要翻译：用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。

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