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71. 发明授权

US5614252A Method of fabricating barium strontium titanate 失效
标题翻译：制造钛酸钡锶的方法
公开(公告)号：US5614252A
公开(公告)日：1997-03-25
申请号：US478398
申请日：1995-06-07
申请人： Larry D. McMillan , Carlos A. Paz de Araujo
发明人： Larry D. McMillan , Carlos A. Paz de Araujo
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/40 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C18/14 , C23C26/02 , C30B7/00 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/115 , H01L41/24 , H05K3/10 , B05D5/12
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/409 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1287 , C23C18/1295 , C23C18/14 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01L21/314 , H01L21/31691 , H01L27/11502 , H01L28/56 , H01L28/60 , H01L41/314 , H01L28/55 , H01L41/1871 , H05K3/105
摘要： A precursor liquid comprising barium and strontium 2-ethylhexanoates and titanium 2-methoxyethanol in a 2-methoxyethanol solvent is prepared, a substrate is placed within a vacuum deposition chamber, the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film of barium strontium titanate on the substrate. Then an integrated circuit is completed to include at least a portion of the layered superlattice material film in a component of the integrated circuit.
摘要翻译：制备在2-甲氧基乙醇溶剂中包含钡和2-乙基己酸锶的前体液体和2-甲氧基乙醇钛，将底物置于真空沉积室内，使前体液体雾化，并将雾流入沉积室，同时将室保持在环境温度下以将一层前体液体沉积在基底上。将液体干燥，烘烤和退火以在基材上形成钛酸钡锶薄膜。然后，完成集成电路以将集成电路的部件中的至少一部分分层超晶格材料膜包括在内。

72. 发明授权

US5559733A Memory with ferroelectric capacitor connectable to transistor gate 失效
标题翻译：具有可连接到晶体管栅极的铁电电容器的存储器
公开(公告)号：US5559733A
公开(公告)日：1996-09-24
申请号：US482765
申请日：1995-06-07
申请人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
发明人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , G11C11/223
摘要： A ferroelectric memory includes a constant voltage source, a capacitor having first and second electrodes, and a transistor having a gate. A switch alternately connects the gate of the transistor to the first electrode and the constant voltage source. In another embodiment, there are two ferroelectric transistors, and the first electrode of each capacitor is connected both to the gate of the transistor and to a voltage source external of the memory.
摘要翻译：铁电存储器包括恒压源，具有第一和第二电极的电容器和具有栅极的晶体管。开关将晶体管的栅极交替地连接到第一电极和恒定电压源。在另一实施例中，存在两个铁电晶体管，并且每个电容器的第一电极都连接到晶体管的栅极和存储器外部的电压源。

73. 发明授权

US5487032A Method and apparatus for reduced fatigue in ferroelectric memory elements 失效
标题翻译：铁电存储元件疲劳减少的方法和装置
公开(公告)号：US5487032A
公开(公告)日：1996-01-23
申请号：US338003
申请日：1994-11-10
申请人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method and apparatus for programming ferroelectric memory cells which reduces fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the rise AC fall times associated with signals used to switch ferroelectric device polarization are shown to reduce fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), are shown to reduce the fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform, a Gaussian signal waveform, and a waveform having exponential rise and fall times are disclosed.
摘要翻译：一种用于编程铁电存储器单元的方法和装置，其减少与诸如铁电电容器和晶体管之类的存储单元相关联的铁电体器件的开关极化的疲劳效应。示出了与用于切换铁电体器件极化的信号相关联的上升AC下降时间的变化，以减少铁电材料的疲劳，从而增加铁电存储器单元的使用寿命。降低上升和下降时间以及信号电平上升和下降（信号形状）的速率，可以减少铁电元件开关极化的疲劳效应。公开了用于产生三角形（“锯齿”）信号波形，高斯信号波形和具有指数上升和下降时间的波形的方法和装置。

74. 发明授权

US5119760A Methods and apparatus for material deposition 失效
标题翻译：材料沉积的方法和装置
公开(公告)号：US5119760A
公开(公告)日：1992-06-09
申请号：US470800
申请日：1990-01-26
申请人： Larry D. McMillan , Carlos A. Paz de Araujo
发明人： Larry D. McMillan , Carlos A. Paz de Araujo
IPC分类号： C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C30B7/00 , H01L21/02 , H01L21/314 , H01L21/316
CPC分类号： C23C16/4558 , C23C16/4412 , C23C16/448 , C23C16/45561 , C23C16/46 , C23C16/482 , C23C16/52 , C30B29/68 , C30B7/00 , C30B7/005 , H01L21/31691 , H01L28/56
摘要： The present invention discloses methods and apparatus for depositing thin films of complex (compound) materials, including ferroelectrics, superconductors, and materials with high dielectric constants through a technique which is hereby entitled photo-enhanced chemical vapor deposition and activation (PECVDA). The technique involves the use of multiple heating sources including a resistive heat bias heater, a tuned optical source (UV or laser) and a source (halogen lamps or microwave sources) for applying high energy, rapid thermal pulses in a precise time sequence.
摘要翻译：本发明公开了通过本文题目为光增强化学气相沉积和激活（PECVDA）的技术，沉积具有高介电常数的铁电体，超导体和材料的复合（复合）材料的薄膜的方法和装置。该技术包括使用多个加热源，包括电阻式热偏置加热器，调谐光源（UV或激光）和源（卤素灯或微波源），用于以精确的时间顺序施加高能量快速热脉冲。

75. 发明申请

US20080107801A1 METHOD OF MAKING A VARIABLE RESISTANCE MEMORY 审中-公开
标题翻译：制造可变电阻记忆体的方法
公开(公告)号：US20080107801A1
公开(公告)日：2008-05-08
申请号：US11937481
申请日：2007-11-08
申请人： Jolanta Celinska , Carlos A. Paz de Araujo , Matthew D. Brubaker
发明人： Jolanta Celinska , Carlos A. Paz de Araujo , Matthew D. Brubaker
IPC分类号： B05D5/12
CPC分类号： H01L45/04 , G11C13/0002 , G11C2213/79 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method of making a variable resistance material (VRM), the method comprising providing a precursor comprising a metallorganic or organometallic solvent containing a metal moiety suitable for forming the VRM, depositing the precursor on a substrate to form a thin film of the precursor, and heating the thin film to form the VRM. The preferred solvent comprises octane.
摘要翻译：一种制备可变电阻材料（VRM）的方法，所述方法包括提供包含含有适于形成VRM的金属部分的金属有机或有机金属溶剂的前体，将前体沉积在基底上以形成前体的薄膜，以及加热薄膜以形成VRM。优选的溶剂包括辛烷。

76. 发明申请

US20080106926A1 NON-VOLATILE RESISTANCE SWITCHING MEMORIES AND METHODS OF MAKING SAME 有权
标题翻译：非易失性电阻开关存储器及其制造方法
公开(公告)号：US20080106926A1
公开(公告)日：2008-05-08
申请号：US11937479
申请日：2007-11-08
申请人： Matthew D. Brubaker , Carlos A. Paz de Araujo , Jolanta Celinska
发明人： Matthew D. Brubaker , Carlos A. Paz de Araujo , Jolanta Celinska
IPC分类号： G11C11/00 , H01L21/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/24 , G11C13/0007 , G11C2213/32 , G11C2213/53 , G11C2213/72 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L29/685 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146
摘要： An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.
摘要翻译：一种集成电路存储单元，包括：具有第一有源区，第二有源区和在有源区之间的沟道的半导体; 以及在通道正上方的可变电阻材料层（VRM）。在一个实施例中，在VRM和沟道之间存在第一导电层，以及VRM层正上方的第二导电层。 VRM优选为相关电子材料（CEM）。存储单元包括FET，例如JFET或MESFET。在另一个实施例中，在VRM和通道之间存在绝缘材料层。在这种情况下，存储单元可以包括MOSFET结构。

77. 发明授权

US06924997B2 Ferroelectric memory and method of operating same 有权
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US06924997B2
公开(公告)日：2005-08-02
申请号：US10381235
申请日：2001-09-25
申请人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan , Yoshihisa Kato , Tatsuo Otsuki , Yasuhiro Shimada
发明人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan , Yoshihisa Kato , Tatsuo Otsuki , Yasuhiro Shimada
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
摘要翻译：铁电存储器636包括一组存储单元（645,12,21,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422， 522等），在其上放置用于将信息写入到存储器单元组的电压，位线（25,49,125,325,425,525等），其中要从该组存储器单元读出的信息放置存储器单元，在存储器单元和位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元之间的设定开关（14,114,314,414,514等）驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。在读取之前，通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。

78. 发明授权

US06781184B2 Barrier layers for protecting metal oxides from hydrogen degradation 有权
标题翻译：用于保护金属氧化物免受氢降解的阻挡层
公开(公告)号：US06781184B2
公开(公告)日：2004-08-24
申请号：US09998469
申请日：2001-11-29
申请人： Narayan Solayappan , Jolanta Celinska , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Narayan Solayappan , Jolanta Celinska , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： H01L27108
CPC分类号： H01L28/57 , H01L23/642 , H01L2924/0002 , H01L2924/00
摘要： A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.
摘要翻译：集成电路中的氢扩散阻挡层位于集成电路中以抑制氢扩散到诸如铁电层状超晶格材料的金属氧化物的薄膜。氢扩散阻挡层包括以下化合物中的至少一种：钽酸锶，钽酸铋，氧化钽，氧化钛，氧化锆和氧化铝。氢阻挡层是无定形的，并且在450℃或更低的温度下通过MOCVD工艺制成。在与所述氢扩散阻挡层相邻的地方形成包括选自氮化硅和所述氢阻挡层材料之一的结晶形式的材料的补充氢阻挡层。

79. 发明授权

US06664115B2 Metal insulator structure with polarization-compatible buffer layer 有权
标题翻译：具有极化兼容缓冲层的金属绝缘体结构
公开(公告)号：US06664115B2
公开(公告)日：2003-12-16
申请号：US09899670
申请日：2001-07-05
申请人： Masamichi Azuma , Carlos A. Paz de Araujo
发明人： Masamichi Azuma , Carlos A. Paz de Araujo
IPC分类号： H01L2100
CPC分类号： H01L21/02304 , C23C16/448 , C23C16/45561 , C23C18/1216 , C23C18/1225 , C23C18/1295 , C23C18/14 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/02197 , H01L21/02282 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/60 , H01L29/78391
摘要： An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a taxis orientation to the final crystal, and results in improved thin-film electrical properties.
摘要翻译： MIS器件（20）包括半导体衬底（22），氮化硅缓冲层（24），铁电金属氧化物超晶格材料（26）和贵金属顶电极（28）。层状超晶格材料（26）优选为钽酸锶锶，铌酸铋锶或钽酸铋铌钽酸锶。根据优选的方法构造器件，其包括在沉积层状超晶格材料之前在半导体衬底上形成氮化硅。层状超晶格材料优选使用液体聚氧化烷基化的金属有机前体沉积，其在加热前体溶液时自发产生层状超晶格。在前体液体的干燥期间的紫外线暴露赋予了最终晶体的出租车方向，并且导致改善的薄膜电性能。

80. 发明授权

US06562678B1 Chemical vapor deposition process for fabricating layered superlattice materials 有权
公开(公告)号：US06562678B1
公开(公告)日：2003-05-13
申请号：US09521094
申请日：2000-03-07
申请人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
发明人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
IPC分类号： H01L218242
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

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