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71. 发明申请

US20100264495A1 High-K Metal Gate CMOS 有权
标题翻译：高K金属门CMOS
公开(公告)号：US20100264495A1
公开(公告)日：2010-10-21
申请号：US12426457
申请日：2009-04-20
申请人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
发明人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.
摘要翻译：提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

72. 发明申请

US20090309228A1 METHOD FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS 有权
标题翻译：形成自对准金属硅化物接触的方法
公开(公告)号：US20090309228A1
公开(公告)日：2009-12-17
申请号：US12539660
申请日：2009-08-12
申请人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
发明人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
IPC分类号： H01L23/532 , H01L21/306
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

73. 发明授权

US07611979B2 Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks 有权
标题翻译：具有低电荷捕获的金属栅极和用于高k栅极电介质叠层的增强的电介质可靠性特性
公开(公告)号：US07611979B2
公开(公告)日：2009-11-03
申请号：US11673901
申请日：2007-02-12
申请人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
发明人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L21/28088 , H01L21/28518 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.
摘要翻译：提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

74. 发明申请

US20090065876A1 Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same 失效
标题翻译：具有减少寄生电容的硅侧壁的金属高K晶体管及其制造方法
公开(公告)号：US20090065876A1
公开(公告)日：2009-03-12
申请号：US11852359
申请日：2007-09-10
申请人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
摘要翻译：公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。耗尽的侧壁层是非晶硅或多晶硅之一。该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

75. 发明申请

US20090039426A1 EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN 有权
标题翻译：具有提高源/漏极值的极性薄膜绝缘体晶体管
公开(公告)号：US20090039426A1
公开(公告)日：2009-02-12
申请号：US11837057
申请日：2007-08-10
申请人： EDUARD A. CARTIER , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
发明人： EDUARD A. CARTIER , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78696
摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.
摘要翻译：提供了一种极薄的绝缘体上硅晶体管，其包括衬底上的掩埋氧化物层，掩埋氧化物层上方的硅层，硅层上的栅极堆叠，硅层上的氮化物衬垫，栅堆叠，氮化物衬垫上并与其相邻的氧化物衬垫，以及升高的源/漏区。栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。凸起的源极/漏极区域中的每一个具有包括硅层的一部分的第一部分，与氧化物衬垫和氮化物衬垫的部分相邻的第二部分，以及在第二部分上方的第三部分。还提供了制造极薄的绝缘体上硅晶体管的方法。

76. 发明申请

US20090001430A1 ELIMINATE NOTCHING IN SI POST SI-RECESS RIE TO IMPROVE EMBEDDED DOPED AND INSTRINSIC SI EPITAZIAL PROCESS 审中-公开
标题翻译：消除注意事项，以改善嵌入式印刷和印刷工艺
公开(公告)号：US20090001430A1
公开(公告)日：2009-01-01
申请号：US11771013
申请日：2007-06-29
申请人： Ashima B. Chakravarti , Renee T. Mo
发明人： Ashima B. Chakravarti , Renee T. Mo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/28176 , H01L29/66636 , H01L29/7848
摘要： A dielectric element, and method of manufacturing the same, is disclosed for a semiconductor structure which comprises a substrate having a gate formed on a top surface of the substrate. The substrate and gate define a gap in a region between the gate and the substrate. A specified amount of dielectric on the substrate, at least a portion of which is in the gap, forms the dielectric element which substantially prevents unwanted electrical connectivity between the gate and the substrate.
摘要翻译：公开了一种用于半导体结构的电介质元件及其制造方法，该半导体结构包括在衬底的顶表面上形成有栅极的衬底。衬底和栅极限定栅极和衬底之间的区域中的间隙。衬底上的至少一部分位于间隙中的指定量的电介质形成基本上防止栅极和衬底之间不必要的电连接的电介质元件。

77. 发明授权

US07446005B2 Manufacturable recessed strained RSD structure and process for advanced CMOS 失效
标题翻译：可制造的凹陷应变RSD结构和高级CMOS工艺
公开(公告)号：US07446005B2
公开(公告)日：2008-11-04
申请号：US11433266
申请日：2006-05-12
申请人： Brian Messenger , Renee T. Mo , Dominic J. Schepis
发明人： Brian Messenger , Renee T. Mo , Dominic J. Schepis
IPC分类号： H01L21/336
CPC分类号： H01L29/66742 , H01L29/7842 , H01L29/78687
摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer severs as a raised layer in which source/drain diffusion regions can be subsequently formed.
摘要翻译：为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。该方法包括在掺杂半导体衬底的表面上形成单层氧和碳; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。应变SiGe层作为凸起层切断，其中可以随后形成源/漏扩散区。

78. 发明授权

US07071072B2 Forming shallow trench isolation without the use of CMP 失效
标题翻译：形成浅沟槽隔离而不使用CMP
公开(公告)号：US07071072B2
公开(公告)日：2006-07-04
申请号：US10710001
申请日：2004-06-11
申请人： Renee T. Mo , Shreesh Narasimha
发明人： Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/76
CPC分类号： H01L21/76283
摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.
摘要翻译：通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

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