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    • 76. 发明授权
    • Method, system, and program for allocating processor resources to a first and second types of tasks
    • 用于将处理器资源分配给第一类和第二类任务的方法,系统和程序
    • US07178147B2
    • 2007-02-13
    • US09960900
    • 2001-09-21
    • Michael Thomas BenhaseYuCheng Hsu
    • Michael Thomas BenhaseYuCheng Hsu
    • G06F9/46
    • G06F9/505
    • Provided is a method, system, and program for allocating processor resources to a first and second types of tasks. An allocation of processor resources to the first and second types of tasks is indicated. Data is gathered indicating a first workload level for the first type of tasks and a second workload level for the second type of tasks. A determination is made of a change to the indicated allocation of processor resources to the first and second types of tasks based on at least one of the first workload level and second workload level data. Tasks of the first type are dispatched to the processor resources allocated to the first type and tasks of the second type are dispatched to the processor resources allocated to the second type.
    • 提供了一种用于将处理器资源分配给第一类和第二类任务的方法,系统和程序。 指示对第一和第二类任务的处理器资源的分配。 收集的数据指示第一类任务的第一工作负载级别和第二类任务的第二工作负载级别。 基于第一工作负载水平和第二工作负载水平数据中的至少一个,确定对所述第一和第二类型的任务的指示的处理器资源分配的改变。 将第一类型的任务分配到分配给第一类型的处理器资源,并且将第二类型的任务分派到分配给第二类型的处理器资源。
    • 77. 发明申请
    • Apparatus, system, and method for time sensitive copy
    • 用于时间敏感拷贝的装置,系统和方法
    • US20060107005A1
    • 2006-05-18
    • US10991940
    • 2004-11-18
    • Herve Gilbert Philippe AndreMichael Thomas BenhaseYu-Cheng HsuDavid Frank Mannenbach
    • Herve Gilbert Philippe AndreMichael Thomas BenhaseYu-Cheng HsuDavid Frank Mannenbach
    • G06F12/16
    • G06F11/1441
    • An apparatus, system, and method are disclosed for copying data from a volatile memory device to a plurality of persistent storage devices in response to a loss of primary power. The apparatus includes a section module, a stripe module, and a write module. The section module sections a data image of a write cache into a plurality of data blocks. The stripe module establishes a plurality of data stripes from the plurality of data blocks. The write module writes in parallel each of the plurality of data stripes to a corresponding plurality of unique, persistent data storage devices in response to a loss of line power to the write cache. Advantageously, the apparatus quickly copies the write data from the write cache to a persistent memory device in a relatively short period of time, decreasing the dependence on significant batteries to back up the volatile memory device.
    • 公开了一种装置,系统和方法,用于将数据从易失性存储器件复制到多个持久存储器件,以响应主电源的损失。 该装置包括部分模块,条带模块和写入模块。 部分模块将写入高速缓存的数据图像分割成多个数据块。 条带模块从多个数据块建立多个数据条带。 响应于对写入高速缓存的线路功率的损失,写入模块将多个数据条带中的每一条并行写入相应的多个唯一的持久数据存储设备。 有利地,该装置在相对短的时间段内将写入数据从写高速缓存快速复制到永久存储器件,减少了对有用电池的依赖以备份易失性存储器件。
    • 79. 发明授权
    • Method and system for caching data in a storage system
    • 存储系统中缓存数据的方法和系统
    • US06658542B2
    • 2003-12-02
    • US10293508
    • 2002-11-13
    • Brent Cameron BeardsleyMichael Thomas BenhaseRobert Louis MortonKenneth Wayne Todd
    • Brent Cameron BeardsleyMichael Thomas BenhaseRobert Louis MortonKenneth Wayne Todd
    • G06F1202
    • G06F11/073G06F11/004G06F11/0724G06F11/0727G06F11/0793G06F12/0804G06F12/0866G06F2212/312
    • Disclosed is a system and method for caching data. A processor receives data from a host to modify a track in a first storage device. The processor stores a copy of the modified data in a cache and indicates in a second storage device the tracks for which there is modified data in cache. During data recovery operations, the processor processes the second storage device and data therein to determine the tracks for which there was modified data in cache. The processor then marks the determined tracks as failed to prevent data at the determined tracks in the first storage device from being returned in response to a read request until the failure is resolved. In further embodiments, in response to detecting a partial failure within the storage system, the processor would scan the cache to determine tracks for which there is modified data stored in the cache. The processor then stores in the second storage device information indicating the tracks having modified data in cache and schedules the destaging of the modified data from the cache to the first storage device. The processor is further capable of receiving and processing read/write requests directed to the first storage device before all the modified data is destaged from cache.
    • 公开了一种用于缓存数据的系统和方法。 处理器从主机接收数据以修改第一存储设备中的轨道。 处理器将修改的数据的副本存储在高速缓存中,并且在第二存储设备中指示在高速缓存中有修改数据的轨道。 在数据恢复操作期间,处理器处理第二存储设备及其中的数据以确定高速缓存中已修改数据的轨道。 然后,处理器将确定的轨道标记为失败,以防止响应于读取请求而返回第一存储设备中确定的轨道上的数据,直到故障被解决为止。 在另外的实施例中,响应于检测存储系统中的部分故障,处理器将扫描高速缓存以确定存储在高速缓存中的修改数据的轨道。 然后,处理器在第二存储设备中存储指示在高速缓存中具有修改数据的轨道的信息,并且将修改后的数据从高速缓存调度到第一存储设备。 在所有修改的数据从缓存中移出之前,处理器还能够接收和处理指向第一存储设备的读/写请求。
    • 80. 发明授权
    • Write data error checking in a PCI Bus system
    • 在PCI总线系统中写入数据错误检查
    • US06530043B1
    • 2003-03-04
    • US09522440
    • 2000-03-09
    • Brent Cameron BeardsleyMichael Thomas BenhaseGregg Steven LucasJuan Antonio Yanes
    • Brent Cameron BeardsleyMichael Thomas BenhaseGregg Steven LucasJuan Antonio Yanes
    • G06F1108
    • H04L1/0061H04L1/0041H04L1/0045
    • In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signals the error.
    • 在PCI总线系统中,方法和系统检查从PCI数据源通过PCI总线传输到PCI总线系统的仪表数据中的错误,该数据包括多个块。 冗余计算逻辑通过PCI总线接收写入数据,计算通过PCI总线传输的数据的每个块的校验值,并且在存储存储器的存储位置处用计算出的校验值更新任何先前计算的校验值。 数据路径逻辑耦合到PCI总线和存储存储器,并且响应在完成跨PCI接口的写入数据传送之后发送的冗余写入命令的唯一标识符。 数据路径逻辑响应写入命令唯一标识符,检测在存储存储器的存储位置处更新的计算的检查值。 耦合到数据路径逻辑的错误检查逻辑确定检测到的更新的计算的检查值是否指示错误,并且在检测到的更新的指示错误的计算的检查值时,发信号通知错误。