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71. 发明申请

US20060031661A1 Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor 有权
标题翻译：读取用于以与wihcih指令中的单元无关的单元执行指令的处理器，以及用于这种处理器的编译器，优化装置，汇编器，链接器，调试器和反汇编器
公开(公告)号：US20060031661A1
公开(公告)日：2006-02-09
申请号：US11245357
申请日：2005-10-07
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/40
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

72. 发明授权

US06964041B2 Processor for making more efficient use of idling components and program conversion apparatus for the same 有权
标题翻译：用于更高效地使用怠速组件和程序转换装置的处理器
公开(公告)号：US06964041B2
公开(公告)日：2005-11-08
申请号：US10653786
申请日：2003-09-03
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3001 , G06F9/3017 , G06F9/3822 , G06F9/3853 , G06F9/3885
摘要： A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.
摘要翻译：具有多个指令槽的处理器，每个指令槽存储要并行执行的指令。多个指令时隙中的一个是第一指令时隙，另一个是第二指令时隙。存储在第一指令槽中的特殊指令由执行存储在第一指令槽中的指令的第一功能单元和执行存储在第二指令槽中的指令的第二功能单元执行。存储在第二指令槽中的指令由执行存储在第二指令槽中的指令的第三功能单元并行执行。

73. 发明授权

US06954820B2 Bus bridge including first and second memory areas corresponding to first and second buses 有权
标题翻译：总线桥包括对应于第一和第二总线的第一和第二存储区域
公开(公告)号：US06954820B2
公开(公告)日：2005-10-11
申请号：US10261797
申请日：2002-09-30
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4059 , G06F13/423 , G06F2213/0024
摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.
摘要翻译：总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

74. 发明申请

US20050177704A1 PROCESSOR FOR MAKING MORE EFFICIENT USE OF IDLING COMPONENTS AND PROGRAM CONVERSION APPARATUS FOR THE SAME 有权
标题翻译：加工者更有效地使用定位部件和程序转换装置
公开(公告)号：US20050177704A1
公开(公告)日：2005-08-11
申请号：US10653786
申请日：2003-09-03
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/3017 , G06F9/3822 , G06F9/3853 , G06F9/3885
摘要： A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.
摘要翻译：具有多个指令槽的处理器，每个指令槽存储要并行执行的指令。多个指令时隙中的一个是第一指令时隙，另一个是第二指令时隙。存储在第一指令槽中的特殊指令由执行存储在第一指令槽中的指令的第一功能单元和执行存储在第二指令槽中的指令的第二功能单元执行。存储在第二指令槽中的指令由执行存储在第二指令槽中的指令的第三功能单元并行执行。

75. 发明授权

US5894135A Superconductor device 失效
标题翻译：超导体器件
公开(公告)号：US5894135A
公开(公告)日：1999-04-13
申请号：US732848
申请日：1996-10-15
申请人： Tetsuya Yamamoto , Hiroshi Suzuki , Kazuhiko Takahashi , Kenichi Kawaguchi , Seiji Suzuki , Yorinobu Yoshisato
发明人： Tetsuya Yamamoto , Hiroshi Suzuki , Kazuhiko Takahashi , Kenichi Kawaguchi , Seiji Suzuki , Yorinobu Yoshisato
IPC分类号： H01L39/22 , H01L29/06
CPC分类号： H01L39/22 , H01L39/223
摘要： A superconductor device comprises a Schottky barrier region S.sub.B for selectively passing injected carriers and a collector barrier region L.sub.B for selectively blocking leakage carriers. The Schottky barrier region is formed in a low permittivity region .epsilon..sub.L between the first operating region (B) made of superconductor material and the second operating region (C) made of either semiconductor material or metallic material. A resonance region R is formed in the low permittivity region .epsilon..sub.L.
摘要翻译：超导体器件包括用于选择性地通过注入的载流子的肖特基势垒区域SB和用于选择性地阻挡泄漏载流子的集电极势垒区域LB。肖特基势垒区形成在由超导体材料制成的第一工作区域（B）和由半导体材料或金属材料制成的第二工作区域（C）之间的低介电常数区域εL中。在低介电常数区域εL中形成共振区域R.

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