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71. 发明授权

US06714075B2 Variable gain amplifier and filter circuit 有权
标题翻译：可变增益放大器和滤波电路
公开(公告)号：US06714075B2
公开(公告)日：2004-03-30
申请号：US10286814
申请日：2002-11-04
申请人： Takashi Morie , Hirokuni Fujiyama
发明人： Takashi Morie , Hirokuni Fujiyama
IPC分类号： H03F345
CPC分类号： H03F3/72 , H03F3/45197 , H03F2203/45648 , H03F2203/45694 , H03F2203/7224 , H03G1/0023 , H03H11/0444 , H03H11/0466 , H03H11/0472
摘要： The variable gain amplifier of the invention includes an input node pair, a first output node pair, a voltage-current converter, a plurality of first resistances, a first current source, a second current source, a second output node pair, a third output node pair and a switch circuit. A differential signal supplied to the input node pair is amplified with a predetermined gain (first gain) and output from the second output node pair. The differential signal is also amplified with a gain (second gain) corresponding to the resistance value between one interconnection node and another interconnection node, among the interconnection nodes connecting the plurality of first resistances, connected to the third output node pair via the switch circuit, and output from the third output node pair. The second gain can be changed by changing the two interconnection nodes connected to the third output node pair via the switch circuit.
摘要翻译：本发明的可变增益放大器包括输入节点对，第一输出节点对，电压 - 电流转换器，多个第一电阻，第一电流源，第二电流源，第二输出节点对，第三输出节点对和开关电路。提供给输入节点对的差分信号以预定增益（第一增益）放大并从第二输出节点对输出。在通过开关电路连接到连接到第三输出节点对的多个第一电阻的互连节点之间，差分信号也被放大为与一个互连节点和另一个互连节点之间的电阻值相对应的增益（第二增益）并从第三输出节点对输出。可以通过改变通过开关电路连接到第三输出节点对的两个互连节点来改变第二增益。

72. 发明授权

US4786953A Vertical MOSFET and method of manufacturing the same 失效
标题翻译：垂直MOSFET及其制造方法
公开(公告)号：US4786953A
公开(公告)日：1988-11-22
申请号：US48702
申请日：1987-05-12
申请人： Takashi Morie , Toshifumi Somatani , Shigeru Nakajima , Kazushige Minegishi , Kenji Miura
发明人： Takashi Morie , Toshifumi Somatani , Shigeru Nakajima , Kazushige Minegishi , Kenji Miura
IPC分类号： H01L29/78 , H01L27/02 , H01L29/04 , H01L29/06
CPC分类号： H01L29/7827
摘要： A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.
摘要翻译：垂直金属氧化物半导体场效应晶体管具有在半导体衬底的主表面上基本上垂直形成的沟槽，形成在包括栅极绝缘膜上的沟槽的侧壁表面的预定区域中的第一导电层，下部和上部扩散形成在沟槽的底部的层和半导体衬底的表面层，优选地形成在上部和下部扩散层之间的半导体衬底中的沟道掺杂区域，以及形成在第二导电层中的下部扩散层并且与第一导电层绝缘以便填充沟槽。第一导电层用作栅电极，扩散层分别用作源/漏区。还提出了制造垂直MOSFET的方法。

73. 发明授权

US4645564A Method of manufacturing semiconductor device with MIS capacitor 失效
标题翻译：使用MIS电容器制造半导体器件的方法
公开(公告)号：US4645564A
公开(公告)日：1987-02-24
申请号：US712860
申请日：1985-03-18
申请人： Takashi Morie , Kazushige Minegishi , Shigeru Nakajima
发明人： Takashi Morie , Kazushige Minegishi , Shigeru Nakajima
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/94 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L29/945 , H01L27/10829 , Y10S148/05
摘要： A semiconductor device with a metal-insulator-semiconductor capacitor has:a semiconductor substrate having a predetermined conductivity type and serving as one electrode of the metal-insulator-semiconductor capacitor, the semiconductor substrate being provided with a trench of a cross-sectionally rectangular shape which extends along a direction of thickness of the semiconductor substrate from a major surface thereof;a doped semiconductor layer formed along at least side wall surfaces of the trench, the semiconductor layer, which is formed by deposition and etching, being provided with an outer surface, starting to extend in a rounded shape from major surface portions of the semiconductor substrate and extending substantially parallel to the side wall surfaces of the trench, and a recess, which is defined by the semiconductor layer, having round corners at the bottom;a dielectric insulating layer formed on an exposed surface including the major surface of the semiconductor substrate and the outer surface of the semiconductor layer; anda conductive layer formed on the insulating layer to bury trench and serving as the other electrode.
摘要翻译：具有金属 - 绝缘体 - 半导体电容器的半导体器件具有：具有预定导电类型并用作金属 - 绝缘体 - 半导体电容器的一个电极的半导体衬底，所述半导体衬底设置有横截面矩形形状的沟槽其从半导体衬底的主表面沿着半导体衬底的厚度方向延伸; 沿着沟槽的至少侧壁表面形成的掺杂半导体层，通过沉积和蚀刻形成的半导体层设置有从半导体衬底的主表面开始以圆形形状延伸的外表面，以及基本上平行于沟槽的侧壁表面延伸，以及由半导体层限定的在底部具有圆角的凹槽; 形成在包括半导体衬底的主表面和半导体层的外表面的暴露表面上的介电绝缘层; 以及形成在绝缘层上以埋设沟槽并用作另一电极的导电层。

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